10-bit DAC with voltage-buffered output
The MAX5521ETC+: The internal reference type means no external reference IC is required; the DAC generates its own full-scale voltage from the supply rails. Architecture is a current-source DAC followed by a voltage buffer — this topology delivers monotonic performance with the ±0.2 LSB DNL figure, which guarantees no missing codes across the full output range.
Settling time and update rate
Typical settling time is 660 µs to 0.5 LSB for a full-scale step — this sets the maximum update rate at roughly 1.5 kHz for a 10-bit output transition. For applications like set-point control in a PID loop or trimming a power supply, this is fast enough for most closed-loop updates. The SPI data interface operates up to the DAC's internal shift-clock limit; the 660 µs settling time, not the SPI clock rate, is the throughput bottleneck.
Housed in a 12-lead WQFN with exposed pad (4x4 mm TQFN footprint per the supplier device package). Tube packaging is standard for this order code; for reel quantities, check the alternate order code suffix at RFQ.