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Analog Devices MAX5441BEUA+ — Analog & Data Acquisition

MAX5441BEUA+ 16-bit DAC, SPI, 1µs settling, 8-uMAX

MPNMAX5441BEUA+
End of Life

Analog Devices MAX5441BEUA+, 16-bit voltage-output DAC, R-2R architecture, SPI interface, 1µs settling time, ±0.5 LSB INL/DNL, 8-uMAX/uSOP package, -40 to +85°C, ROHS3.

$22.3Ref. price · indicative, final on quote
Packaging8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
StockContact for availability
Lead time3-5 Days wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
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Specifications

MAX5441BEUA+ Technical Specifications
ParameterValue
Output typeVoltage - Unbuffered
Mounting typeSurface Mount
Reference typeExternal
Voltage - supply, analog5V
Voltage - supply, digital5V
InterfaceSPI
Operating temperature-40°C ~ 85°C
PackageTube
ArchitectureR-2R
INL (DNL)±0.5, ±0.5
Settling time1µs (Typ)
Number of bits16
Case8-TSSOP, 8-MSOP (0.118\", 3.00mm Width)
Differential outputNo
Number of d (A converters)1

Product details

16-bit precision on a single 5 V rail

The MAX5441BEUA+ is a 16-bit, voltage-unbuffered DAC from Analog Devices that settles to within ±0.5 LSB in 1 µs typical — fast enough for closed-loop servo and ATE pin-driver updates without waiting on the analog bus. It runs on a single 5 V supply for both the analog and digital sections, so you don't need a separate AVDD/DVDD pair or a charge pump. The external reference (REF) sets the full-scale output, which means the same BOM can serve multiple output spans by swapping the reference voltage.

R-2R ladder — monotonic by design

The R-2R resistor-ladder architecture gives inherently monotonic transfer: every increase in digital code produces a corresponding increase in analog output, with no missing codes. Because the output is unbuffered, the DAC's output impedance is the R-2R ladder's own (~10 kΩ typical). That means it drives a high-impedance load (like an op-amp input or a comparator) directly, but for a 50 Ω or 75 Ω terminated line you need an external buffer. The trade-off is lower power and no buffer-induced offset error.

SPI interface and package fit

The SPI data interface uses a standard 3-wire (SCLK, DIN, CS) protocol. Multiple MAX5441 devices can share the same bus in a daisy-chain or individual chip-select topology — useful for multi-channel analog output cards where you want to minimise the number of digital isolator channels. The exposed pad on the underside is not present — this is a standard 8-lead MSOP with no thermal slug, so the power dissipation is limited to about 0.5 W at 85°C ambient without airflow.

That means it's safe to qualify into a new design today and expect multi-year production availability. ROHS3 compliant (exemption-free per EU 2015/863), so it ships without any of the restricted substances and doesn't trigger the 0.1% threshold reporting that ROHS2 exemptions can cause.

Frequently asked questions

What is the settling time of the MAX5441BEUA+ and why does it matter?

1 µs typical to ±0.5 LSB. This sets the maximum update rate: at 1 µs settle time, you can update the DAC at roughly 1 MSPS (mega-sample per second) assuming the SPI clock can keep up. For a servo loop with a 10 kHz bandwidth, the DAC settles in 1% of the loop period — plenty of margin.

Can I use the MAX5441BEUA+ with a 3.3 V digital supply?

No — the digital supply (DVDD) is specified at 5 V, same as the analog supply. The part does not have a separate low-voltage digital rail. If your microcontroller runs at 3.3 V, you need a level translator on the SPI lines or a 5 V-tolerant MCU.