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Analog Devices MAX503CWG+T — Discrete Semiconductors

Analog Devices MAX503CWG+T DAC, 10-bit, Voltage-Out, 24-SOIC

MPNMAX503CWG+T
End of Life

Analog Devices MAX503CWG+T, 10-bit voltage-output DAC, R-2R architecture, parallel interface, ±0.5 LSB INL, 25 µs settling, 24-SOIC wide-body, Tape & Reel.

$3.91324Ref. price · indicative, final on quote
Packaging24-SOIC (0.295", 7.50mm Width)
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

MAX503CWG+T Technical Specifications
ParameterValue
Output typeVoltage - Buffered
Mounting typeSurface Mount
Reference typeExternal, Internal
Voltage - supply, analog±5V
Voltage - supply, digital5V
InterfaceParallel
Operating temperature0°C ~ 70°C
PackageTape & Reel (TR)
ArchitectureR-2R
INL (DNL)±0.5 (Max), ±1 (Max)
Settling time25µs (Typ)
Number of bits10
Case24-SOIC (0.295\", 7.50mm Width)
Differential outputNo
Number of d (A converters)1

Product details

10-bit DAC with R-2R core and voltage-buffered output

The MAX503CWG+T is a single-channel 10-bit digital-to-analog converter from Analog Devices, built on an R-2R ladder architecture with an internal output buffer. It delivers a voltage output that can directly drive an ADC input or analog control node without an external op-amp stage. Resolution is 10 bits — 1024 distinct output levels — with integral nonlinearity (INL) held to ±0.5 LSB maximum and differential nonlinearity (DNL) within ±1 LSB maximum. The R-2R topology guarantees monotonicity across the full code range, so no missing codes occur at the 10-bit level.

Settling time and interface — what limits the update rate

Output settling time is 25 µs typical to ±0.5 LSB for a full-scale step. This sets the maximum update rate at roughly 40 kHz for full-swing transitions, though smaller code steps settle faster. For a control loop updating at 10 kHz, the DAC has adequate margin. The data interface is parallel — all 10 bits are latched simultaneously on a single write strobe. No serial clock overhead, so the bus write time is one memory-cycle wide, suitable for DSP or microcontroller parallel ports.

Supply rails and reference options

Analog supply is ±5 V, digital supply is 5 V — these are the only rails required. The reference can be either external (applied to the REF pin) or internal (the on-chip bandgap). Using the internal reference simplifies the BOM by one reference IC but ties the full-scale voltage to the bandgap tolerance; an external reference lets the user set the output span to match the ADC's input range.

Package and assembly — 24-SOIC wide-body

The wide-body SOIC footprint is standard for reflow assembly; the reel format suits automated pick-and-place for volume production. Mounting is surface-mount only. The 24-SOIC body width requires a pad pattern matching the 7.50 mm package — verify the board layout accepts this footprint before specifying.

Production status is Active — the MAX503CWG+T is in current manufacture with no announced end-of-life. ROHS3 compliant (no exemptions).

Frequently asked questions

What is the INL/DNL specification of the MAX503CWG+T?

INL is ±0.5 LSB maximum, DNL is ±1 LSB maximum. The R-2R architecture ensures monotonicity — no missing codes at 10-bit resolution.

What supply voltages does the MAX503CWG+T require?

Analog supply is ±5 V, digital supply is 5 V. The part also supports an external or internal voltage reference.