115k SPS, 16-bit SAR ADC with integrated PGA
The MAX1301BEUP+ is a 16-bit successive-approximation-register (SAR) ADC from Analog Devices, sampling at 115k samples per second. The SAR architecture delivers a single-cycle conversion with no pipeline delay, making it a direct fit for multiplexed measurement systems where each channel must be read and settled before the next conversion starts. Its internal configuration — MUX-PGA-S/H-ADC — integrates a 2- or 4-channel input multiplexer and a programmable-gain amplifier (PGA) ahead of the sample-and-hold and the SAR core. This means a single device handles signal scaling and channel selection over the SPI bus, reducing the external analog front-end count.
Input flexibility and signal-chain integration
The ADC accepts both differential and single-ended inputs, selectable per configuration. With differential inputs, the common-mode rejection rejects ground offsets and noise picked up on long sensor leads — useful for bridge sensors or thermocouple interfaces where the signal is a few millivolts above a noisy return. The on-chip PGA amplifies small signals before the SAR conversion, effectively increasing the dynamic range for low-level inputs. The reference can be supplied externally or drawn from the internal reference, giving the designer control over the full-scale range without adding an external reference IC. Analog and digital supplies both run from a single 5 V rail, simplifying the power tree. The SPI data interface operates at speeds that keep up with the 115k SPS throughput — the serial clock must complete 16 bits plus any overhead within each sampling period.
Package, temperature grade, and lifecycle
The 0.65 mm pitch and standard TSSOP footprint are layout-friendly for two-layer boards with adequate decoupling close to the supply pins.