ADC core and sampling architecture
The MAX1198ECM+D is an 8-bit pipelined ADC from Analog Devices that samples at 100 MSPS (100 million samples per second) — this is the sustained conversion rate, not a burst mode, so it captures a continuous 100 MHz-wide Nyquist zone without dead cycles between conversions. Two internal A/D converters sample simultaneously via a 1:1 S/H-ADC ratio per channel — the dual 100 MSPS path means a single MAX1198 captures two independent analog signals at full rate, useful for I/Q demodulation or dual-channel data acquisition where timing skew between channels must stay below one clock cycle.
Signal input and reference flexibility
Each of the two inputs accepts either differential or single-ended signals — a common IF or baseband front-end can drive the ADC directly without an external balun if the signal is already differential, or with a single-ended-to-differential converter if it is not. The reference can be supplied externally or generated internally, which simplifies board routing when the reference voltage is shared across multiple converters. The parallel data interface outputs all 8 bits per conversion on a single 8-bit bus — for dual-channel mode the part interleaves the two channels on alternating clock edges, so the downstream FPGA or DSP must latch the data at the correct edge. The bus is standard 3.3 V CMOS, compatible with most 3.3 V logic families without a level shifter.