480 SPS sample rate and noise floor trade-off
The MAX11200EEE+: The 480 SPS maximum sample rate is the output data rate after the internal digital filter. For a 24-bit converter, the usable throughput is lower than the raw rate because the filter settling time must complete before a valid conversion is read. At 480 SPS the -3 dB bandwidth is roughly 0.262 × the output rate, or about 126 Hz — adequate for DC and low-frequency AC measurements. Dropping the sample rate reduces noise; the datasheet noise floor at 10 SPS is typically several times lower than at 480 SPS, which matters when the input signal is a microvolt-level bridge output. The differential input rejects common-mode noise picked up on long sensor leads — a 60 Hz hum on both lines cancels before the modulator. The external reference lets the designer set the full-scale range independently of the supply rails, which is useful when the sensor output is ratiometric to the excitation voltage.
Supply rails and digital interface flexibility
This split-rail architecture means the ADC can operate with a 3.3 V analog section and a separate 1.8 V digital I/O rail, eliminating the need for a level translator between the ADC and a 1.8 V host microcontroller. The 16-SSOP and 16-QSOP packages share the same 3.90 mm body width and 0.635 mm lead pitch — the QSOP is a thinner-profile variant.