12-bit SAR ADC at 1 Msps — the speed-resolution tradeoff
The MAX11128ATI+ is a 12-bit successive-approximation-register (SAR) ADC from Analog Devices, sampling at 1 Msps — fast enough to digitize a 500 kHz analog signal at Nyquist, or oversample a slower sensor channel for noise reduction. The SAR architecture gives you a deterministic conversion time with no pipeline delay, so the sample timing is predictable in a control loop.
Input mux flexibility — 8, 15, or 16 channels
The input multiplexer can be configured as 8 differential, 15 pseudo-differential, or 16 single-ended channels — the same silicon handles all three topologies, so one BOM line serves multiple board variants by changing the firmware configuration. The MUX-S/H-ADC signal chain (1:1 S/H-to-ADC ratio) means each channel gets a dedicated sample-and-hold before conversion, avoiding crosstalk between adjacent inputs during the acquisition window. Reference type is external — you supply the VREF pin with the voltage that sets the full-scale range. This lets you scale the input span to match the sensor output (e.g., 2.5 V for a ratiometric bridge, 3.3 V for a 0-10 V divider) without losing LSB resolution. The external reference also means the ADC's gain accuracy tracks the reference drift, not an internal bandgap.
The SPI data interface requires four wires — SCLK, DIN, DOUT, and CS — plus the VREF and supply pins. No parallel bus or external timing controller needed, so the routing stays tight around the ADC on a 2-layer board if the ground plane is continuous under the package.
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