What this clock buffer does at 1.4 GHz
The LTC6954IUFF-4#PBF is a single-channel fanout buffer with an integrated divider, accepting LVCMOS, LVDS, or LVPECL inputs and delivering LVCMOS or LVDS outputs at a maximum frequency of 1.4 GHz. The 1:3 ratio means one input drives three output paths — useful for splitting a reference clock to multiple ADCs, FPGAs, or SerDes transceivers without adding jitter from a separate PLL.
Industrial temperature grade and supply rails
The supply voltage range is tight at 3.15V to 3.45V — plan a clean 3.3V rail with ±5% tolerance; a switching regulator with 50 mV ripple will eat into that margin.
Package and footprint for layout
Housed in a 36-WFQFN with exposed pad, 4 mm x 7 mm body. Surface-mount only; no through-hole option.
Active production — no EOL concern
For BOM planning, this line item is stable — no forced redesign or last-time buy horizon.
