Active production, 2 MSPS simultaneous-sampling SAR ADC
The LTC2321CUFD-12#PBF: Each ADC runs at 2 MSPS, giving a 4 MSPS aggregate throughput when both channels are active. The 12-bit resolution yields 4096 codes; at 2 MSPS the conversion time is deterministic with no pipeline delay, making this part suitable for applications that need a known latency per sample.
Dual-supply rails and input flexibility for the layout engineer
The part requires two supply rails: an analog supply of 3.13 V to 3.47 V (typically 3.3 V) and a 5 V rail that powers the input front-end. The digital interface shares the same 3.13 V to 3.47 V range, so the SPI or LVDS output levels match the 3.3 V logic domain without an external level shifter. The input stage accepts either differential or pseudo-differential signals. In differential mode, the ADC rejects common-mode noise on the signal pair; in pseudo-differential mode, one input is tied to a reference (e.g., AGND or VCM) and the other carries the signal, saving one pin per channel at the cost of some noise immunity. The reference can be either the internal 2.5 V bandgap or an external precision reference driven into the REF pin. Using the internal reference simplifies the BOM; an external reference improves drift and accuracy if the system already carries a stable voltage source.
28-QFN exposed-pad package — thermal and footprint notes
The LTC2321CUFD-12#PBF comes in a 28-lead WFQFN with an exposed pad (4 mm × 5 mm body). The exposed paddle on the bottom of the package must be soldered to a copper land on the PCB — this provides the primary thermal path for heat dissipation and also serves as the analog ground connection. A thermal via array under the pad is recommended to conduct heat to the inner ground plane. The part is shipped in a Tube, not tape-and-reel. For the rework lab, the QFN package requires a hot-air reflow profile with a peak temperature around 260 °C per JEDEC J-STD-020; the exposed pad needs a solder paste stencil aperture that covers at least 50% of the pad area to ensure void-free solder joint formation.
Dual-mode digital interface: LVDS or standard serial
The digital output can be configured for LVDS (low-voltage differential signaling) or standard CMOS serial. LVDS provides noise-immune data transfer over longer traces or through a cable, at the cost of requiring external 100-Ω termination resistors at the receiver. Standard serial mode uses a single-ended data line and a conversion clock, compatible with most MCU SPI ports.