25 MSPS, 16-bit — where the speed meets the noise floor
The LTC2160IUK#PBF is a 16-bit pipelined ADC sampling at 25 MSPS with a differential input — the 25 MSPS rate is the ceiling for capturing fast transients in a single channel, while the 16-bit resolution gives you 96 dB of theoretical dynamic range before the noise floor of the front-end amplifier dominates.
Package and board-fit — 48-QFN with exposed pad
The LVDS - Parallel data interface gives you a choice: run the output as a serial LVDS pair to save trace count, or switch to parallel CMOS for simpler FPGA glue logic. The 1:1 S/H:ADC ratio means no interleaving artifacts — one sample per clock edge.
