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Analog Devices LTC1657CGN#PBF — Discrete Semiconductors

LTC1657CGN#PBF 16-Bit DAC, 28-SSOP, Voltage Output, Active

MPNLTC1657CGN#PBF
End of Life

Analog Devices LTC1657CGN#PBF, 16-bit voltage-output DAC, 28-SSOP, String DAC architecture, parallel interface, ±4 LSB INL, 20 µs settling, tube.

$20.82Ref. price · indicative, final on quote
Packaging28-SSOP (0.154", 3.90mm Width)
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

LTC1657CGN#PBF Technical Specifications
ParameterValue
Output typeVoltage - Buffered
Mounting typeSurface Mount
Reference typeExternal, Internal
Voltage - supply, analog5V
Voltage - supply, digital5V
InterfaceParallel
Operating temperature0°C ~ 70°C
PackageTube
ArchitectureString DAC
INL (DNL)±4, ±0.5
Settling time20µs (Typ)
Number of bits16
Case28-SSOP (0.154\", 3.90mm Width)
Differential outputNo
Number of d (A converters)1

Product details

16-bit resolution and linearity for precision analog output

The LTC1657CGN#PBF is a single-channel 16-bit digital-to-analog converter with voltage-buffered output, built on a String DAC architecture. Its 16-bit resolution provides 65,536 discrete output levels from a 5 V analog supply — each LSB step is roughly 76 µV, which matters when the downstream ADC or comparator needs fine-grained setpoint control without post-filter gain. Integral nonlinearity is ±4 LSB maximum, and differential nonlinearity is ±0.5 LSB maximum — the DNL spec guarantees monotonicity, so every code increment produces a positive voltage step. This is essential for closed-loop systems where a non-monotonic DAC could cause the loop to hunt or latch. Settling time is 20 µs typical to ±0.5 LSB, which sets a practical update rate around 50 kHz. For waveform generation or servo setpoint updates, the system clock must budget this delay between write cycles.

Parallel interface with 5 V rails — legacy bus ready

Data is written via a parallel interface — all 16 bits are latched in one write cycle, no serial clock needed. This suits DSP or FPGA buses that already have a 16-bit data path and can drive the control signals without an SPI or I²C wrapper. Both analog and digital supply rails are 5 V (nominal), so no separate level translator is required when the host logic also runs at 5 V. The reference can be external or internal, giving flexibility to scale the output range. Packaged in a 28-lead SSOP (0.154-inch body width, 3.90 mm), surface-mount. The tube delivery suits medium-volume pick-and-place; the 0.0256-inch pin pitch is compatible with standard 0.65 mm pitch SSOP footprints.

Temperature grade and compliance

Rated for the commercial temperature range of 0°C to 70°C. This limits deployment to controlled indoor environments — industrial enclosures with ambient above 70°C or outdoor telecom shelters would need a wider-temperature variant.

Frequently asked questions

How does LTC1657CGN#PBF compare to AD5640CRMZ-2?

The AD5640CRMZ-2 is a 14-bit DAC (vs 16-bit), uses an SPI interface (vs parallel), and has a wider temperature range of -40°C to 105°C (vs 0°C to 70°C). If your design needs the extra resolution and a parallel bus, the LTC1657CGN#PBF is the correct fit; if you can accept 14 bits and prefer serial communication with wider temperature coverage, the AD5640CRMZ-2 is an alternative.