25 MHz 8051 core, ROMless — external code store required
The DS80C320-QCG+T&R is an 8-bit microcontroller built around the 8051 core, clocked at 25 MHz. It executes standard 8051 instructions at a higher throughput per cycle than the original architecture, but the part is ROMless — no on-chip program memory. All code must reside in external EPROM, Flash, or OTP accessed through the external bus interface (EBI/EMI). On-chip RAM is 256 x 8 bytes, matching the classic 8051 register file and scratchpad layout. The 32 I/O lines are shared with the external bus and serial ports; a design using the full EBI for code fetch will consume most of Port 0 and Port 2, leaving fewer pins for general-purpose I/O.
Supply rail, temperature grade, and package
The commercial temperature range is 0°C to 70°C, suitable for indoor, non-condensing environments. No industrial or automotive grade is listed. Packaged in a 44-lead PLCC with J-leads (44-LCC), surface-mount. The supplier device package is 44-PLCC (16.59 x 16.59 mm). The J-lead footprint is common in through-hole-solder reflow and socketed applications; the PLCC socket is a standard off-the-shelf item.
On-chip peripherals: watchdog and power-fail reset
The integrated watchdog timer (WDT) and power-fail reset provide basic supervisory coverage. The WDT can reset the core if firmware stalls; the power-fail reset generates an early warning interrupt before the supply drops below the operating threshold, allowing the firmware to save critical state to external non-volatile memory. Serial connectivity includes a UART/USART and SIO, plus the external bus for memory and peripheral expansion. The oscillator is external — a crystal or ceramic resonator must be provided; no internal RC oscillator is present.
Sourced through independent distribution channels.