Active and ready for BOM insertion
The DS1804-050+: It carries ROHS3 compliance, so no regulatory restriction on where it ships or what it goes into.
What the 100-tap linear taper means for your circuit
The DS1804-050+ is a single-channel digital potentiometer with a linear taper and 100 wiper tap positions. The 50kΩ end-to-end resistance is divided into 100 steps, giving roughly 500 Ω per step — enough resolution for gain trimming, offset nulling, or adjustable voltage dividers in analog signal chains. The wiper resistance is 400 Ω typical, which sets a floor on the minimum output impedance when the wiper is at either end of the resistive element. The ±20% tolerance on the total resistance is typical for digital pots — the ratiometric accuracy between tap positions is tighter than the absolute value, so the part works well as a voltage divider even if the absolute resistance varies from lot to lot.
Non-volatile wiper position and 3-wire interface
The memory type is non-volatile, meaning the wiper position is stored when power is removed and recalled at power-up. The control interface is a simple 3-wire Up/Down protocol: Chip Select (CS), Increment (INC), and Up/Down (U/D). This uses fewer GPIO pins than a SPI or I²C pot and is straightforward to bit-bang from any logic device.
Through-hole package and temperature range
The DS1804-050+ comes in an 8-pin DIP package (0.300-inch width), with the supplier device package specified as 8-PDIP. The through-hole form factor is breadboard-friendly and easy to hand-solder or socket in prototype runs, and equally suitable for wave-solder production. The temperature coefficient is 750 ppm/°C typical. For a 50kΩ pot, that is roughly 37.5 Ω/°C drift on the total resistance — the ratiometric drift between taps is lower, but worth noting if the pot sets an absolute current or voltage that must stay stable across temperature.