Silicon delay line — 5 taps, 50 ns total
The DS1100LZ-50+ is a nonprogrammable 5-tap silicon delay line delivering a total delay of 50 ns from input to final tap, with a fixed 10 ns increment between taps. The single independent delay line provides five equally spaced outputs, each referenced to the input with a delay accuracy determined by the tap increment. The 10 ns step suits timing alignment in clock distribution or pulse-width adjustment where sub-100 ns resolution is needed.
Surface-mount assembly in the 8-SOIC footprint (0.154" body width) with tube packaging. The package is standard for low-pin-count timing ICs and reflows on the same profile as other SOIC-8 passives and logic.
Lifecycle and compliance
For new designs, confirm the tap count and total delay match the timing budget; the nonprogrammable function means the delay profile is fixed at manufacture.