Dual SPDT CMOS switch — 45Ω on-resistance, 150ns switching
The Analog Devices DG403CY+ is a dual SPDT CMOS analog switch with two independent circuits, each configured as a 2:1 multiplexer/demultiplexer (SPDT). It switches signals up to the supply rails with a maximum on-state resistance of 45Ω and channel-to-channel matching of 500mΩ — the matching figure matters when routing precision analog signals where gain/offset consistency between channels is critical. Switching time is 150ns max on (Ton) and 100ns max off (Toff), fast enough for audio crosspoint switching, data acquisition channel sequencing, or ATE pin electronics. Off-leakage is specified at 500pA max, and channel capacitance is 12pF (both CS(off) and CD(off)) — these keep the signal integrity clean in high-impedance sample-and-hold or multiplexed ADC front-ends. Crosstalk is rated at -90dB at 1MHz, meaning the feedthrough from one channel to the other is suppressed by 90dB at that frequency — a strong spec for audio or low-frequency instrumentation where channel separation is non-negotiable. Charge injection is 10pC, low enough that glitch energy on the output during switching stays small for moderate source impedances.
Operates from a single supply of 10V to 30V or dual supplies of ±4.5V to ±20V — the wide range covers standard ±5V, ±12V, ±15V analog rails as well as single 12V, 15V, or 24V industrial supplies.
This is a standard narrow-body SOIC footprint, 1.27mm pitch, compatible with typical 16-pin SOIC land patterns. No special reflow profile beyond standard JEDEC MSL-1 (moisture sensitivity level not stated, but the package is common and usually MSL-1).
Active lifecycle — ROHS3 compliant
ROHS3 compliant (lead-free, no exemptions per the ROHS3 directive). This is a current-production part, not an obsolete or NRND line item.