LVDS isolation for high-speed differential links
It supports a 600 Mbps data rate per channel and provides 5000 Vrms isolation — the rating that determines creepage and clearance for reinforced isolation in mains-referenced systems.
The 5000 Vrms isolation voltage is the peak test withstand, not the working voltage — for reinforced-grade designs you still need to check the working voltage derating curve in the datasheet for the target lifetime. The 25 kV/µs common-mode transient immunity (CMTI) is the real-world spec that matters when the isolator sits on a motor phase or a half-bridge node: fast voltage swings across the barrier can couple through parasitic capacitance and corrupt the LVDS eye if the CMTI isn't high enough. At 25 kV/µs minimum, this part handles the edge rates in SiC and GaN inverter stages without bit errors.
Propagation delay and signal-integrity budget
Maximum propagation delay is 4.5 ns in each direction, with rise and fall times of 0.35 ns. That 4.5 ns adds to the link timing budget — in a closed-loop control application with a 600 Mbps serial stream, the combined delay and jitter must leave enough setup-and-hold margin at the receiver. The 0.35 ns edge rates also demand careful PCB layout: controlled-impedance traces and a solid ground plane under the LVDS pair, with the supply decoupling placed close to the 2.375 V to 2.625 V supply pins.