400 MHz PLL with bypass – what it does for your RF loop
The ADF4002BRUZ is a PLL clock/frequency synthesizer with a phase detector and a bypass mode, targeting RF synthesizer and clock clean-up applications where the reference runs up to 400 MHz. The integrated PLL includes a charge pump and a programmable divider, but the bypass path lets you feed the reference clock straight through when the loop is not needed — useful for test modes or redundant clock paths.
Supply and temperature – fits 3.3V industrial designs
Runs on a single 2.7V to 3.3V rail, matching the common 3.3V supply used in base station and wireless infrastructure boards. Inputs accept CMOS or TTL levels, so you can interface directly with a crystal oscillator or a 3.3V FPGA output without external level shifting. The single-ended clock output is also CMOS/TTL-compatible.
Package and footprint – 16-TSSOP layout note
Housed in a 16-TSSOP package with 0.65 mm lead pitch, the ADF4002BRUZ fits a standard 4.40 mm-wide body. The supplier device package is also 16-TSSOP; no exposed pad, so a 2-layer board with a solid ground plane under the device is adequate for thermal management at the rated supply current.