RF PLL clock generator for 200 MHz reference synthesis
The ADF4001BCPZ-RL7 is a frequency synthesizer built around a phase-locked loop (PLL) — it takes a CMOS or TTL reference input and generates a clean 200 MHz clock output for RF local-oscillator or data-converter clocking. Supply range 2.7V to 5.5V lets it drop into a 3.3V or 5V rail without a secondary regulator; the differential input/output option (Yes/No) means single-ended is the default, so check your signal path.
200 MHz ceiling and divider flexibility
Maximum output frequency is 200 MHz — sufficient for IF synthesis or clocking a 14-bit ADC up to ~100 MSPS. The divider (Yes) allows integer-N division of the VCO frequency, while the multiplier (No) means no fractional-N capability. Two input pins feed one clock output (2:1 ratio), so you can switch between a local oscillator and an external reference without an external mux.
Active production — no last-time-buy pressure
Lifecycle status is Active — no PCN, no EOL notice, no LTB deadline. ROHS3 compliant and the 20-LFCSP (4x4) package has an exposed pad that needs a thermal land on the PCB — plan for a via array under the paddle.
Industrial temperature range and package fit
Package is 20-LFCSP (4x4) with exposed pad. Surface-mount only; the pitch requires a soldermask-defined pad and a 4-layer board for the ground plane connection to the paddle.