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Analog Devices ADCMP565BPZ — Logic ICs

ADCMP565BPZ dual comparator with latch

MPNADCMP565BPZ
End of Life

Analog Devices ADCMP565BPZ, dual ultra-fast comparator with latch, 375 ps propagation delay, ±1 mV hysteresis, complementary ECL/open-emitter outputs, 20-PLCC (9x9) surface mount, -40°C to 85°C.

$16.23Ref. price · indicative, final on quote
Packaging20-LCC (J-Lead)
StockContact for availability
MOQ1 pcs
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Specifications

ADCMP565BPZ Technical Specifications
ParameterValue
Typewith Latch
Output typeComplementary, Differential, ECL, Open-Emitter
Mounting typeSurface Mount
Voltage - input offset6mV @ 5V
Voltage - supply, single (Dual (±))±4.75V ~ 5.25V
Current - output30mA
Current - quiescent18mA, 80mA
Current - input bias40µA @ 5V
Operating temperature-40°C ~ 85°C
PackageTube
Hysteresis±1mV
Case20-LCC (J-Lead)
CMRR, PSRR69dB CMRR
Number of elements2
Propagation delay0.375ns

Product details

375 ps — what that delay means for your signal chain

The ADCMP565BPZ is Analog Devices' dual ultra-fast comparator with a maximum propagation delay of 0.375 ns (375 ps). That places it in the class of comparators used for time-of-flight measurements, high-speed line receivers, and pulse-width discriminator front-ends where a few hundred picoseconds of skew can flip a bit. The 375 ps figure is the max over temperature and supply, not a typical — the 20-PLCC package adds about 50 ps of trace delay per side from the bond wire, so factor that into your timing budget if the output drives a distant line.

ECL outputs — termination is not optional

The output type is complementary, differential, ECL, open-emitter. That means the outputs are emitter-follower stages that need a pull-down resistor to the negative supply rail (typically -2 V or ground-referenced with a Thevenin termination). No internal pull-up exists — leave the emitter open and the output floats high. The 30 mA typical output current drives 50 Ω loads into -2 V cleanly. If your design expects a TTL or LVCMOS level, this part requires a translator or a PECL termination network to shift the levels. The latch input holds the state on the rising edge of the latch-enable pin; leave it unconnected or tie high for transparent mode.

Supply rails and quiescent budget

The quiescent current splits into two rails: 18 mA on one, 80 mA on the other (the ECL output stage draws the larger share). Total around 98 mA worst-case, which is modest for a dual 375 ps comparator but not a low-power part. The ±1 mV hysteresis is built in, so you do not need external positive feedback resistors to clean up noisy edges. Input offset voltage maxes at 6 mV at 5 V supply, and input bias current at 40 µA — both typical for a high-speed bipolar comparator. CMRR is 69 dB typical.

Package and rework profile

The 20-PLCC (J-lead) package is a known quantity — no BGA reball or hot-air profile guesswork. The leads are on the perimeter, visible for inspection, and the J-lead form is forgiving of board flex. The 9x9 mm body in the supplier device package field matches the industry-standard PLCC-20 footprint. The mounting type is surface mount, and the shipping medium is tube, not tape and reel.

Frequently asked questions

What is the propagation delay of the ADCMP565BPZ?

The maximum propagation delay is 0.375 ns (375 ps) over temperature and supply. This is the worst-case spec, not a typical — the actual delay at 25°C is usually lower.

What is the output type of the ADCMP565BPZ?

The outputs are complementary, differential, ECL, open-emitter. They require external pull-down resistors to the negative supply rail to function — no internal pull-up exists.