7.5 GHz clock distribution in a 3x3 mm footprint
The ADCLK914BCPZ-R7 is a 1:1 clock buffer/driver from Analog Devices' SiGe series, rated for a maximum frequency of 7.5 GHz. That speed ceiling makes it a fit for distributing high-frequency reference clocks to ADCs, DACs, and SERDES transceivers where edge jitter and deterministic skew matter more than fan-out count. It accepts a wide range of input signal types — CML, CMOS, LVDS, LVPECL, and LVTTL — and outputs HVDS. The supply range is 2.97V to 3.63V, so it runs on a single 3.3V rail with margin for ripple. The 1:1 input-to-output ratio means it is a pure buffer — no division, no multiplication — just clean regeneration of the incoming clock.
Temperature grade and package constraints
The exposed pad is also the ground return for the high-speed signal path — a poor thermal connection here degrades both thermal impedance and signal integrity. For a rework tech: this is a QFN-style package; hot-air removal is routine, but the pad under the centre can be stubborn if the board has a thick ground plane. Pre-bake at 125°C for 8 hours if the parts have been exposed to humidity above MSL level 3.
It is ROHS3 compliant and available in tape-and-reel (TR) or cut-tape (CT) packaging. For volume BOM planning, this is a single-source part from ADI — no direct second-source with the same 7.5 GHz rating and multi-protocol input is listed.