The ADCLK905BCPZ-R2 is a single-channel clock buffer from Analog Devices' SiGe family, designed to distribute high-frequency clock or data signals with minimal additive jitter. It accepts a differential clock input and delivers a differential output at ECL, NECL, or PECL levels — the output logic family is set by the supply voltage and termination scheme. With a maximum frequency of 7.5 GHz, this part targets RF test equipment, high-speed ADC clock distribution, optical transceiver modules, and broadband data buffering where signal integrity at multi-GHz rates is non-negotiable.
Supply range and temperature grade — design margin
The supply voltage spans 2.375 V to 3.63 V, covering both 2.5 V and 3.3 V nominal rails. This eliminates the need for a dedicated regulator when the board already carries one of those voltages — a practical BOM simplification.
Package and footprint — 16-LFCSP with exposed pad
Housed in a 16-lead LFCSP (3 mm × 3 mm) with an exposed pad, the package requires a thermal via array under the pad to conduct heat to the PCB ground plane. The small footprint saves board area in dense RF layouts.
Active production — no obsolescence pressure
There is no end-of-life notice or last-time-buy deadline — it remains a supported, orderable part for new and existing designs.