PLL clock generator for multi-rate line cards
The AD9577BCPZ is a dual-PLL clock generator from Analog Devices, purpose-built for Ethernet, PCI Express, and SONET/SDH line cards. It accepts a clock or crystal input and delivers up to five outputs in LVCMOS, LVDS, or LVPECL logic families — covering the three most common backplane clocking standards from a single IC. Maximum output frequency is 637.5 MHz, which covers PCIe Gen3/4 reference clocks and 10GBASE-R line rates. The 2:5 input-to-output ratio means you can distribute one or two reference sources to five downstream PLLs or SerDes without an external fanout buffer.
Output flexibility and supply rail
Each output bank can be independently configured for LVCMOS, LVDS, or LVPECL — a single BOM position handles mixed-logic clock trees. The supply range is 3.0 V to 3.6 V, which aligns with standard 3.3 V backplane rails; no additional LDO is needed for the clock IC. Differential inputs are not supported (the input side is single-ended clock or crystal), but all five outputs can be differential (LVDS or LVPECL). This matters when the reference source is a local oscillator and the fanout targets differential SerDes reference inputs.
Active production and package details
Housed in a 40-lead LFCSP-WQ (6x6 mm) with an exposed pad.