PLL clock generator with bypass — what it covers
The AD9552BCPZ-REEL7 is a single-channel clock generator from Analog Devices that accepts either a CMOS or crystal input and delivers a differential output in CMOS, LVDS, or LVPECL format. The integrated PLL includes a bypass mode, letting you feed a clean reference straight through when the loop is not needed. Maximum output frequency is 900 MHz, which covers most gigabit-serDes reference clocks, FPGA transceiver reference paths, and ADC/DAC sample clocks up to that ceiling.
Output format flexibility and supply tolerance
Three output standards — CMOS, LVDS, LVPECL — let the same part drive a 50-ohm terminated LVPECL trace, a differential LVDS pair, or a single-ended CMOS load without a separate level translator. The 2:2 input-to-output ratio means two clock inputs can be selected and two outputs are available, though only one PLL core is present.
Active status and package for production planning
ROHS3 compliant, which simplifies EU and RoHS-restricted-market BOM compliance. Housed in a 32-lead LFCSP-WQ (5x5 mm) with an exposed pad for thermal management. Quoted to order against your BOM quantity.