900 MHz PLL clock generator with bypass
The AD9552BCPZ is a single-circuit clock generator from Analog Devices, integrating a PLL with a bypass option so you can switch between a clean on-chip synthesis path and an external reference clock without reconfiguring the board. It accepts CMOS or crystal inputs and delivers CMOS, LVDS, or LVPECL outputs up to 900 MHz, covering the common telecom and data-converter clock rates.
2:2 input-to-output ratio and differential output
With a 2:2 input-to-output ratio, the AD9552BCPZ accepts two single-ended references and produces two outputs — both can be configured as differential (LVDS or LVPECL) to drive long traces or high-speed ADCs. The PLL bypass path lets one output run as a clean buffer while the other remains PLL-locked, useful for clock-domain separation in mixed-signal systems.
Active production, 32-LFCSP package
The small footprint and 0.50 mm pitch require a well-planned thermal via array under the pad for heat sinking; the datasheet layout recommendation is worth following closely.
