What the 800 MHz ceiling means for your clock tree
The AD9513BCPZ is a 1:3 fanout buffer with a maximum frequency of 800 MHz. That 800 MHz ceiling sets the upper bound for distributing a reference clock to ADCs, DACs, or FPGAs. The 1:3 ratio means one input drives three outputs, which is enough for a three-channel receiver chain or a master clock fan-out to a PLL, an FPGA, and a test point. Both input and output paths are differential, which buys common-mode rejection on the clock line — important when the clock trace runs past a switching regulator or a noisy digital bus. The output can be configured as CMOS or LVDS, so you can match the logic family of the downstream device without an external level translator.
Supply rail and temperature range
The 32-VFQFN exposed pad package must be soldered to a ground plane for thermal and electrical performance.
