1.2 GHz fanout buffer with three output standards
The AD9512BCPZ is a clock fanout buffer and divider from Analog Devices, rated for a maximum input frequency of 1.2 GHz. It accepts two clock inputs and distributes them to five outputs, each independently programmable to CMOS, LVDS, or LVPECL levels. The 2:5 fanout ratio means a single reference clock can feed five downstream devices — an ADC, an FPGA, a SerDes, a DAC, and a monitor port — all from one buffer, saving board space and reducing clock-tree jitter from multiple discrete fanout gates.
Output flexibility — CMOS, LVDS, LVPECL per channel
Each of the five outputs can be set to CMOS, LVDS, or LVPECL independently, so a mixed-signal board with a CMOS FPGA input, an LVDS ADC clock, and an LVPECL SerDes reference can all be driven from the same buffer without external translators. The input and output paths are fully differential, which gives better common-mode noise rejection than single-ended clock distribution — important when routing clocks across a noisy mixed-signal board.
Package and footprint — 48-LFCSP with exposed pad
Housed in a 48-lead LFCSP (7x7 mm) with an exposed pad, the package requires a thermal land on the PCB to pull heat from the die. Surface-mount only — the LFCSP demands a controlled solder-paste stencil and a reflow profile that matches the package's moisture sensitivity level.