{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"ZL30256LFG7","brand":"Microchip Technology","brandSlug":"microchip","productSlug":"ZL30256LFG7","canonicalUrl":"https://icboms.com/microchip/ZL30256LFG7","factsUrl":"https://icboms.com/api/mcp/products/ZL30256LFG7","rawCanonicalId":null},"summary":{"shortDescription":"Microchip Technology ZL30256LFG7 jitter attenuator, PLL-based, 1.045 GHz max, 10:18 I/O, 3 circuits, CMOS/HCSL/HSTL/LVDS/LVPECL outputs, 80-LGA (11x11 mm), tray.","salesMarkdown":"## PLL-based jitter cleaning for high-speed clocks The ZL30256LFG7 is a PLL-based jitter attenuator from Microchip, designed to clean up noisy clock sources in high-speed digital systems. It accepts a single-ended CMOS input and can produce up to 18 outputs in any mix of CMOS, HCSL, HSTL, LVDS, or LVPECL standards — covering the common logic families used on a typical FPGA or SerDes reference clock tree. With a maximum output frequency of 1.045 GHz, this part handles 10G-class SerDes reference clocks and high-speed ADC/DAC sample clocks. The three independent PLL circuits let you clean multiple clock domains from a single device, reducing board space and BOM count compared to using separate attenuators per rail. ## 80-LGA package and board integration The 1.71V–1.89V core supply and 3.135V–3.465V I/O supply rails are separate, so you can run the core at 1.8V while the outputs swing at 3.3V to match downstream logic levels. The differential input and output capability means it can accept and deliver LVDS or LVPECL signals directly, avoiding external level translators.","metaTitle":"Microchip ZL30256LFG7 Jitter Attenuator, 1.045 GHz, 80-LGA","metaDescription":"Active PLL-based jitter attenuator from Microchip. 10:18 I/O ratio, 1.045 GHz max, 3 circuits, -40 to 85°C. 80-LGA (11x11 mm). Quoted to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Discrete Semiconductors"],"specifications":{"PLL":"Yes","Type":"Jitter Attenuator","Input":"CMOS","Output":"CMOS, HCSL, HSTL, LVDS, LVPECL","Package":"Tray","Mounting Type":"Surface Mount","Package / Case":"80-VFLGA","Frequency - Max":"1.045GHz","lifecycle_stage":"eol_hot","Voltage - Supply":"1.71V ~ 1.89V, 3.135V ~ 3.465V","Divider/Multiplier":"Yes/No","Number of Circuits":"3","Ratio - Input:Output":"10:18","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"80-LGA (11x11)","Differential - Input:Output":"Yes/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$31.46","priceTiers":[{"qty":1,"price":"$31.46000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/9ad59bdb3bf465a54ea95c29f7c976d9.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/ZL30256LFG7/alternatives.json"},"ai":{"faq":[{"question":"What output standards does the ZL30256LFG7 support?","answer":"The device outputs CMOS, HCSL, HSTL, LVDS, and LVPECL. This covers the common clock formats for FPGAs, SerDes, and high-speed converters, so you can drive multiple logic families from one attenuator."},{"question":"What is the maximum frequency the ZL30256LFG7 can generate?","answer":"The maximum output frequency is 1.045 GHz, which covers 10G-class SerDes reference clocks and high-speed ADC/DAC sample rates."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/microchip/ZL30256LFG7","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/microchip/ZL30256LFG7 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}