{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"ZL30145GGG2","brand":"Microchip Technology","brandSlug":"microchip","productSlug":"ZL30145GGG2","canonicalUrl":"https://icboms.com/microchip/ZL30145GGG2","factsUrl":"https://icboms.com/api/mcp/products/ZL30145GGG2","rawCanonicalId":null},"summary":{"shortDescription":"Microchip Technology ZL30145GGG2 DPLL, Ethernet/SONET/SDH/Telecom, PLL Yes, Input Clock, Output Clock, 622.08MHz max, 1 circuit, 1:3 ratio, 64-CABGA, Tray.","salesMarkdown":"## 622.08 MHz DPLL for line-card timing The ZL30145GGG2: This is a digital PLL (DPLL) with a 622.08 MHz maximum output frequency — the exact rate for OC-12/STM-4 in SONET/SDH transport. The 1:3 input-to-output ratio means one reference clock feeds three synthesized outputs, which is typical for fanning timing to multiple line-card PHYs or framers. The differential output (No/Yes) means the input side accepts single-ended clock references while the output side drives differential signals — CML or LVPECL levels, depending on the downstream load. That saves an external clock buffer when the PHY expects a differential input. The 64-CABGA (9x9 mm) package is a standard BGA footprint — 0.8 mm pitch typical for this ball count, which a 4-layer board can route without microvias. ## Compliance and documentation The standard compliance package (RoHS, REACH, conflict minerals reporting) is available with the shipment documentation.","metaTitle":"Microchip ZL30145GGG2 DPLL, 622.08MHz, 64-CABGA","metaDescription":"Active Microchip ZL30145GGG2 DPLL for Ethernet, SONET/SDH, Telecom. 622.08MHz max, 64-CABGA, -40 to 85°C. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Discrete Semiconductors"],"specifications":{"PLL":"Yes","Input":"Clock","Output":"Clock","Package":"Tray","Main Purpose":"Ethernet, SONET/SDH, Telecom","Mounting Type":"Surface Mount","Package / Case":"64-BGA","Frequency - Max":"622.08MHz","lifecycle_stage":"eol_hot","Number of Circuits":"1","Ratio - Input:Output":"1:3","Operating Temperature":"-40°C ~ 85°C","Supplier Device Package":"64-CABGA (9x9)","Differential - Input:Output":"No/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$26.96","priceTiers":[{"qty":1,"price":"$26.96000","currency":"USD"}]},"links":{"datasheetUrl":null,"sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/ZL30145GGG2/alternatives.json"},"ai":{"faq":[{"question":"Who supplies ZL30145GGG2 and how is it quoted for volume purchases?","answer":"Sourced through independent distribution against an RFQ."},{"question":"What is ZL30145GGG2's listed PLL on this Discrete Semiconductors line?","answer":"The PLL field is Yes — this is a digital PLL (DPLL) device, not a standalone VCO or clock buffer. It synthesizes output clocks from an input reference using an internal loop filter."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/microchip/ZL30145GGG2","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/microchip/ZL30145GGG2 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}