{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"XC9572XL-10VQG64I","brand":"AMD","brandSlug":"amd","productSlug":"XC9572XL-10VQG64I","canonicalUrl":"https://icboms.com/amd/XC9572XL-10VQG64I","factsUrl":"https://icboms.com/api/mcp/products/XC9572XL-10VQG64I","rawCanonicalId":null},"summary":{"shortDescription":"AMD XC9500XL CPLD, XC9572XL-10VQG64I, 72 macrocells, 10 ns pin-to-pin delay, 52 I/O, 3.0 V – 3.6 V supply, -40 °C to +85 °C, 64-VQFP (10x10), Tray.","salesMarkdown":"## 72 macrocells at 10 ns — what the delay means for the firmware engineer The XC9572XL-10VQG64I: Its headline spec is a 10 ns pin-to-pin propagation delay (tpd) — this means combinatorial logic paths settle within one 100 MHz clock period, so a state machine or glue-logic decode that crosses the chip in a single cycle has 10 ns of budget before the next clock edge. For the firmware bring-up engineer, that 10 ns window sets the timing closure floor: any path exceeding it must be pipelined or split across two macrocells. ## 52 I/O and 1600 gates — board-fit for the layout engineer 52 user I/O are available in a 64-VQFP (10x10 mm) package — the 0.50 mm pitch demands a 4-layer board for clean fan-out of the inner rows, though the outer two rows break out on two layers if the routing is short. The 1600 usable gates map to the 72 macrocells; each macrocell can be configured as combinatorial or registered logic. Within the XC9500XL family, the -10 speed grade (10 ns tpd) sits between the -7 (7 ns, faster) and -15 (15 ns, slower) variants. The -10 is the most commonly stocked speed bin — it meets 100 MHz logic without the premium of the -7 grade. For a BOM cost engineer, the -10 is typically the price/performance sweet spot in this family; the -7 adds cost for timing margin that most glue-logic designs do not need.","metaTitle":"AMD XC9572XL-10VQG64I CPLD, 72 macrocells, 10 ns, 64-VQFP","metaDescription":"AMD XC9572XL-10VQG64I CPLD: 72 macrocells, 10 ns pin-to-pin delay, 52 I/O, 3.0-3.6 V, -40 to +85 °C, 64-VQFP. Active, RoHS3. Sourced to order.","metaKeywords":null},"attributes":{"series":"XC9500XL","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"AMD","Series":"XC9500XL","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"52","Package / Case":"64-TQFP","Product Status":"Active","Number of Gates":"1600","lifecycle_stage":"unknown","Programmable Type":"In System Programmable (min 10K program/erase cycles)","Base Product Number":"XC9572","Number of Macrocells":"72","Delay Time tpd(1) Max":"10 ns","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"64-VQFP (10x10)","Voltage Supply - Internal":"3V ~ 3.6V","Number of Logic Elements/Blocks":"4"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$14.2800","priceTiers":[{"qty":1,"price":"$14.28000","currency":"USD"}]},"links":{"datasheetUrl":null,"sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/XC9572XL-10VQG64I/alternatives.json"},"ai":{"faq":[{"question":"What is the pin-to-pin delay on the XC9572XL-10VQG64I?","answer":"The maximum pin-to-pin propagation delay (tpd) is 10 ns. This is the time from a registered input through combinatorial logic to a registered output — the figure that sets the system clock ceiling for single-cycle paths."},{"question":"How many I/O pins does the XC9572XL-10VQG64I have?","answer":"52 user I/O are available in the 64-VQFP package. The remaining 12 pins are dedicated to power, ground, JTAG, and global control signals."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/amd/XC9572XL-10VQG64I","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/amd/XC9572XL-10VQG64I when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}