{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"SN74LS73AD","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"SN74LS73AD","canonicalUrl":"https://icboms.com/texas-instruments/SN74LS73AD","factsUrl":"https://icboms.com/api/mcp/products/SN74LS73AD","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments 74LS series SN74LS73AD dual JK flip-flop, negative-edge trigger, reset function, complementary outputs, 45 MHz clock frequency, 14-SOIC surface-mount package.","salesMarkdown":"## Active 74LS dual JK flip-flop — timing and BOM fit The SN74LS73AD is an active-production dual JK flip-flop from Texas Instruments' 74LS low-power Schottky family, clocked at 45 MHz with a 20 ns max propagation delay into 15 pF at 5 V. That 20 ns window sets the timing margin for a synchronous design — the clock-to-Q delay plus setup time on the next stage must close within one clock period. At 45 MHz the period is roughly 22 ns, leaving just 2 ns of slack before the output misses the next edge. The 6 mA quiescent current is the idle draw; the output stage can source 400 µA and sink 8 mA per pin, enough to drive one or two standard TTL loads but not a high-fanout bus without buffering. ## 14-SOIC surface-mount — board integration note Housed in a 14-SOIC package (3.90 mm body width, 0.154-inch pitch), the SN74LS73AD sits on a standard SOIC-14 footprint shared with dozens of logic ICs. The supplier device package is 14-SOIC, so the land pattern matches JEDEC MS-012 — no special copper pad or thermal management required for a 6 mA part. Tube shipment means the parts arrive in anti-static tubes; for reeled volume the order code may differ. ## RoHS3 compliant — regulatory acceptance Texas Instruments lists the SN74LS73AD as ROHS3 Compliant, covering the full RoHS exemption set including lead in solder for high-reliability applications.","metaTitle":"SN74LS73AD Dual JK Flip-Flop, 45 MHz, 14-SOIC","metaDescription":"Active Texas Instruments SN74LS73AD dual JK flip-flop, 45 MHz clock, 20ns propagation delay, 14-SOIC surface mount. RoHS3 compliant. Quoted to order.","metaKeywords":null},"attributes":{"series":"74LS","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Analog & Data Acquisition"],"specifications":{"Type":"JK Type","Series":"74LS","Package":"Tube","Function":"Reset","Output Type":"Complementary","Trigger Type":"Negative Edge","Mounting Type":"Surface Mount","Package / Case":"14-SOIC (0.154\\\", 3.90mm Width)","Clock Frequency":"45 MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"4.75V ~ 5.25V","Number of Elements":"2","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"14-SOIC","Current - Quiescent (Iq)":"6 mA","Current - Output High, Low":"400µA, 8mA","Number of Bits per Element":"1","Max Propagation Delay @ V, Max CL":"20ns @ 5V, 15pF"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$2.45","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$2.45000","currency":"USD"},{"qty":10,"price":"$2.19700","currency":"USD"},{"qty":25,"price":"$2.07240","currency":"USD"},{"qty":100,"price":"$1.76560","currency":"USD"},{"qty":250,"price":"$1.65784","currency":"USD"},{"qty":500,"price":"$1.45060","currency":"USD"},{"qty":1000,"price":"$1.20193","currency":"USD"},{"qty":2500,"price":"$1.17300","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/acb88f37abd70372fc5168ec938eb7d0.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Will the SN74LS73AD drop into a board designed for the SN74HCS74QBQARQ1?","answer":"No. The SN74HCS74QBQARQ1 is an automotive-grade 74HC-series D-type flip-flop in a different package and with a positive-edge trigger. The SN74LS73AD is a JK-type flip-flop with negative-edge trigger and a reset function — the pinout, logic function, and trigger edge are incompatible without a board spin."},{"question":"What is the clock frequency and propagation delay of the SN74LS73AD?","answer":"The maximum clock frequency is 45 MHz. The max propagation delay is 20 ns at 5 V with a 15 pF load — this is the time from the clock edge to the output transition, and it sets the timing closure budget for downstream logic."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/SN74LS73AD","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/SN74LS73AD when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}