{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"SN74LS175NS","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"SN74LS175NS","canonicalUrl":"https://icboms.com/texas-instruments/SN74LS175NS","factsUrl":"https://icboms.com/api/mcp/products/SN74LS175NS","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments 74LS series D-Type flip-flop, SN74LS175NS, positive-edge triggered, master reset, complementary outputs, 40 MHz clock, 25ns propagation delay @ 5V/15pF, 4.75V–5.25V supply, 0°C–70°C, 16-SOIC package.","salesMarkdown":"## What this 74LS quad D-type flip-flop does on the board Each of the four flip-flops captures data on the positive edge of the clock and presents both true and complementary outputs, saving an external inverter for inverted-signal paths. A common master-reset line asynchronously clears all four flip-flops, which is useful for power-on initialization or system reset without cycling the clock. The part is rated for commercial temperature range (0°C to 70°C) and runs on a 5 V supply (4.75 V to 5.25 V), typical for legacy 5 V TTL backplanes and control logic. ## 40 MHz clock and 25 ns propagation delay — what they mean for timing closure The 40 MHz maximum clock frequency sets the upper bound for synchronous data transfer through this flip-flop. The 25 ns propagation delay (at 5 V, 15 pF load) is the number to check against the setup-and-hold requirements of the receiving device downstream.","metaTitle":"SN74LS175NS D-Type Flip-Flop, 40 MHz, 16-SOIC, 74LS Series","metaDescription":"SN74LS175NS from Texas Instruments 74LS series, D-type positive-edge triggered flip-flop with master reset and complementary outputs.","metaKeywords":null},"attributes":{"series":"74LS","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Logic ICs"],"specifications":{"Type":"D-Type","Series":"74LS","Package":"Bulk","Function":"Master Reset","Output Type":"Complementary","Trigger Type":"Positive Edge","Mounting Type":"Surface Mount","Package / Case":"16-SOIC (0.209\\\", 5.30mm Width)","Clock Frequency":"40 MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"4.75V ~ 5.25V","Number of Elements":"1","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"16-SO","Current - Quiescent (Iq)":"18 mA","Current - Output High, Low":"400µA, 8mA","Number of Bits per Element":"4","Max Propagation Delay @ V, Max CL":"25ns @ 5V, 15pF"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$0.46","priceTiers":[{"qty":656,"price":"$0.46000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/d412137535796406c27b759cffc8ef83.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/SN74LS175NS/alternatives.json"},"ai":{"faq":[{"question":"Is SN74LS175NS equivalent to SN74LS175D?","answer":"The SN74LS175D is the SOIC-16 version of the same quad D-type flip-flop. The SN74LS175NS uses the same 16-SOIC package and same 74LS die, so they are functionally identical and pin-compatible. The difference is only in the ordering code suffix."},{"question":"What is the difference between SN74LS175 and SN74LS175A?","answer":"The SN74LS175A is an improved version with tighter propagation delay specifications and typically lower power consumption. The SN74LS175NS (the standard SN74LS175) has a 25 ns max delay at 5 V/15 pF; the 'A' variant generally offers faster switching. Both are 5 V, positive-edge triggered, quad D-types with master reset and complementary outputs."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/SN74LS175NS","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/SN74LS175NS when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}