{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"SN65LVDS18DRFRG4","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"SN65LVDS18DRFRG4","canonicalUrl":"https://icboms.com/texas-instruments/SN65LVDS18DRFRG4","factsUrl":"https://icboms.com/api/mcp/products/SN65LVDS18DRFRG4","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments SN65LVDS18DRFRG4, single-channel Buffer/ReDriver, PECL input, LVDS output, 2 Gbps data rate, 460 ps delay, 2.375 V to 3.6 V supply, 8-WFDFN exposed pad / 8-WSON (2x2 mm), -40°C to 85°C, Tape & Reel.","salesMarkdown":"## PECL-to-LVDS signal conditioner in a 2x2 mm package It is designed for high-speed serial links where signal integrity degrades over backplane traces or cables — the reDriver reshapes the edge rates and re-transmits a clean LVDS swing, effectively extending the reach of a PECL source without a separate PLL or retimer. Rated for a maximum data rate of 2 Gbps with a typical propagation delay of 460 ps, the part fits 1 GbE, SATA Gen 1, and general-purpose clock/data distribution up to 2 Gbps. The closest pin-compatible alternative in the same functional family would be the SN65LVDS18 (non-RG4 suffix) or a cross from a second-source vendor such as Onsemi or Microchip — but each has its own supply and temperature-grade profile. Validate the replacement against your signal-level and timing budget before committing the BOM line. ## Signal translation and timing budget The PECL input threshold is referenced to a 3.3 V or 2.5 V PECL swing; the LVDS output drives a 100 Ω differential termination with a typical 350 mV swing. The 460 ps propagation delay adds to the overall link latency — budget it in your timing closure for source-synchronous interfaces where the clock and data paths must match within a few hundred picoseconds. The single-channel topology means one PECL pair in, one LVDS pair out. For multi-drop or multi-lane applications, you need one device per lane. The 2 Gbps data rate is the maximum specified — derate for cable losses or connector discontinuities; the reDriver does not recover the clock, so jitter accumulates across cascaded stages.","metaTitle":"TI SN65LVDS18DRFRG4 PECL-to-LVDS Buffer/ReDriver, 2 Gbps","metaDescription":"Texas Instruments SN65LVDS18DRFRG4 single-channel PECL-to-LVDS buffer/reDriver. 2 Gbps data rate, 460 ps delay, 2.375-3.6 V supply, 8-WSON package.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Interface & Transceivers"],"specifications":{"Mfr":"Texas Instruments","Type":"Buffer, ReDriver","Input":"PECL","Output":"LVDS","Series":"-","Package":"Tape & Reel (TR)","Delay Time":"460ps","Applications":"-","Mounting Type":"Surface Mount","Package / Case":"8-WFDFN Exposed Pad","Product Status":"Obsolete","Data Rate (Max)":"2Gbps","lifecycle_stage":"eol_hot","Current - Supply":"30mA","Voltage - Supply":"2.375V ~ 3.6V","Number of Channels":"1","Base Product Number":"SN65L","Signal Conditioning":"-","Operating Temperature":"-40°C~85°C","Supplier Device Package":"8-WSON (2x2)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/036fed4f756f90d64598dd4beddef1df.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the replacement for SN65LVDS18DRFRG4?","answer":"No official replacement order code is recorded. The base part SN65LVDS18 (non-RG4 suffix) is the same die in a different packaging option, but its lifecycle status should be verified independently. For a pin-compatible alternative, evaluate the SN65LVDS18 or a cross from Onsemi/Microchip in the same PECL-to-LVDS buffer family, confirming supply voltage range and data rate."},{"question":"What is the data rate performance of SN65LVDS18DRFRG4?","answer":"This supports 1 GbE, SATA Gen 1, and other serial links up to 2 Gbps."},{"question":"What is the input signal type for SN65LVDS18DRFRG4?","answer":"The input signal type is PECL (Positive Emitter-Coupled Logic). The output is LVDS (Low-Voltage Differential Signaling)."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/SN65LVDS18DRFRG4","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/SN65LVDS18DRFRG4 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}