{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"SN65LVDS105DR","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"SN65LVDS105DR","canonicalUrl":"https://icboms.com/texas-instruments/SN65LVDS105DR","factsUrl":"https://icboms.com/api/mcp/products/SN65LVDS105DR","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments SN65LVDS105DR, LVDS Buffer/Multiplexer, LVTTL input, LVDS output, 1 x 1:4, 400Mbps data rate, 2.2ns delay, 3V–3.6V supply, -40°C to 85°C, 16-SOIC package.","salesMarkdown":"At 400 Mbps the SN65LVDS105DR can serialize a 40 MHz parallel bus into a single LVDS pair, or distribute a 200 MHz clock with sub-3 ns edge-to-edge skew across four outputs. The 2.2 ns propagation delay is the time from input crossing to output valid; in a clock tree this adds to the overall skew budget, so if you are fanning out a 100 MHz clock to multiple receivers, account for the delay mismatch between this buffer and any other devices in the path. The 3 pF input capacitance is light enough that a single LVTTL source can drive it without extra buffering. ## Supply rails and signal levels The LVTTL input threshold is compatible with 3.3 V logic families; the LVDS output delivers a differential swing of roughly 350 mV into a 100 Ω termination, standard for LVDS receivers. No external bias resistors needed on the output side — the driver handles the common-mode voltage internally.","metaTitle":"SN65LVDS105DR LVDS Buffer/Multiplexer, 400 Mbps, 16-SOIC","metaDescription":"TI SN65LVDS105DR LVTTL-to-LVDS buffer/multiplexer with 1:4 fanout, 400 Mbps data rate, 2.2 ns delay, -40°C to 85°C. Active lifecycle, available to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Interface & Transceivers"],"specifications":{"Mfr":"Texas Instruments","Type":"Buffer, Multiplexer","Input":"LVTTL","Output":"LVDS","Series":"-","Package":"Tape & Reel (TR)","Delay Time":"2.2ns","Applications":"-","Mounting Type":"Surface Mount","Package / Case":"16-SOIC (0.154\\\", 3.90mm Width)","Product Status":"Active","Data Rate (Max)":"400Mbps","lifecycle_stage":"eol_hot","Current - Supply":"23mA","Voltage - Supply":"3V ~ 3.6V","Number of Channels":"1 x 1:4","Base Product Number":"65LVDS105","Capacitance - Input":"3 pF","Signal Conditioning":"-","Operating Temperature":"-40°C ~ 85°C","Supplier Device Package":"16-SOIC"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$2.5173","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/e176d556db021e219f412862e30d08f1.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/SN65LVDS105DR/alternatives.json"},"ai":{"faq":[{"question":"What is the data rate of SN65LVDS105DR?","answer":"Rated for 400 Mbps maximum, which corresponds to a 200 MHz clock frequency if used as a clock buffer. The 2.2 ns propagation delay and 3 pF input capacitance help maintain signal integrity at that speed."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/SN65LVDS105DR","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/SN65LVDS105DR when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}