{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"SN65LVDS101DR","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"SN65LVDS101DR","canonicalUrl":"https://icboms.com/texas-instruments/SN65LVDS101DR","factsUrl":"https://icboms.com/api/mcp/products/SN65LVDS101DR","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments SN65LVDS101DR Buffer, ReDriver, Input CML/LVDS/LVPECL, Output LVPECL, 2 Gbps max data rate, 630 ps delay, 8-SOIC package, -40°C to 85°C, 3V to 3.6V supply.","salesMarkdown":"## Single-channel signal conditioner for high-speed serial links It is designed for serial links where the signal has degraded over a backplane or cable — the device reshapes the waveform and re-drives it without retiming, adding only 630 ps of propagation delay. Typical deployment is in telecom infrastructure, base stations, and high-speed data-acquisition systems where a 2 Gbps data rate must be maintained across a few metres of FR4 or a connector. ## Input protocol flexibility and output standard The input stage handles three common differential signalling standards — CML, LVDS, and LVPECL — without external level-shifting resistors. This makes the SN65LVDS101DR a universal buffer for mixed-protocol environments: a serializer with CML outputs can drive an LVPECL clock fanout tree, or an LVDS backplane receiver can be repeated as LVPECL into a PLL. The output is fixed to LVPECL, which provides a larger differential swing (typically 800 mV) than LVDS, useful when driving long traces or multiple AC-coupled loads. ## 2 Gbps data rate and 630 ps delay — timing budget considerations Rated for a maximum data rate of 2 Gbps, the part covers common serial standards up to 2.5 Gbps with margin (e.g., 1.25 Gbps XAUI, 2.125 Gbps Fibre Channel). The 630 ps propagation delay is deterministic and adds to the total link latency; in a round-trip timing budget for a clock-forwarded interface, that 630 ps is the per-device contribution. The 0.6 pF input capacitance is low enough that it does not load the driving source appreciably at these frequencies. ## Supply and current draw That is the total current for the whole channel — no separate output bias supply needed. The 8-SOIC package dissipates the heat adequately in still air up to 85°C ambient; if the ambient pushes above 70°C in a confined enclosure, a small airflow or a heatsink on the board plane helps keep the junction below the maximum. TI lists the SN65LVDS101DR as Active.","metaTitle":"SN65LVDS101DR Buffer, ReDriver, 2 Gbps, 8-SOIC","metaDescription":"TI SN65LVDS101DR is a single-channel Buffer/ReDriver accepting CML, LVDS, LVPECL inputs, outputting LVPECL at up to 2 Gbps. 630 ps delay.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Interface & Transceivers"],"specifications":{"Mfr":"Texas Instruments","Type":"Buffer, ReDriver","Input":"CML, LVDS, LVPECL","Output":"LVPECL","Series":"-","Package":"Tape & Reel (TR)","Delay Time":"630ps","Applications":"-","Mounting Type":"Surface Mount","Package / Case":"8-SOIC (0.154\\\", 3.90mm Width)","Product Status":"Active","Data Rate (Max)":"2Gbps","lifecycle_stage":"eol_hot","Current - Supply":"50mA","Voltage - Supply":"3V ~ 3.6V","Number of Channels":"1","Base Product Number":"65LVDS101","Capacitance - Input":"0.6 pF","Signal Conditioning":"-","Operating Temperature":"-40°C~85°C","Supplier Device Package":"8-SOIC"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$3.0090","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/504e0dff2bc3612f9257686fcd8fe425.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/SN65LVDS101DR/alternatives.json"},"ai":{"faq":[{"question":"Does SN65LVDS101DR have any direct replacements or equivalents?","answer":"The base product number 65LVDS101 covers multiple variants within the same family, but a direct drop-in replacement from another manufacturer is not documented. For dual-sourcing, check other members of the 65LVDS101 family that share the same input/output standards and package."},{"question":"What signals can be input to SN65LVDS101DR?","answer":"The input stage accepts CML, LVDS, and LVPECL differential signals. No external level translation is needed between these three standards."},{"question":"What is the output signal type of SN65LVDS101DR?","answer":"The output is LVPECL, providing a differential swing typically around 800 mV."},{"question":"Does SN65LVDS101DR support 2 Gbps data rate?","answer":"Yes, the maximum data rate is 2 Gbps. The 630 ps propagation delay is deterministic and adds to the link latency."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/SN65LVDS101DR","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/SN65LVDS101DR when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}