{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"MT55L256L18P1F-10","brand":"Micron Technology","brandSlug":"micron","productSlug":"MT55L256L18P1F-10","canonicalUrl":"https://icboms.com/micron/MT55L256L18P1F-10","factsUrl":"https://icboms.com/api/mcp/products/MT55L256L18P1F-10","rawCanonicalId":null},"summary":{"shortDescription":"Micron ZBT® SRAM, MT55L256L18P1F-10, 4Mbit (256K x 18), 5 ns access time, 100 MHz clock, parallel interface, 3.135V–3.465V supply, 0°C to 70°C, 165-FBGA (13x15 mm).","salesMarkdown":"The Micron MT55L256L18P1F-10 is a 4 Mbit ZBT (Zero Bus Turnaround) synchronous SRAM organized as 256K x 18 bits. It is designed for high-throughput applications where back-to-back read and write cycles must occur without dead cycles — think packet buffers in network switches, cache in telecom line cards, or look-up tables in FPGA-based accelerators. The 5 ns access time and 100 MHz clock rate let it keep pace with a 100 MHz bus without wait states, so timing closure on a high-speed memory interface is straightforward. ## Package and mounting — 165-ball FBGA The 165-ball TBGA (13x15 mm body) is a fine-pitch BGA that requires a multi-layer PCB with via-in-pad or microvia routing. It is surface-mount only — no socket option. The commercial temperature range (0°C to 70°C) limits this part to indoor, climate-controlled environments like central-office telecom, data-center networking gear, or benchtop test equipment. Not rated for industrial or automotive use. ## Lifecycle and sourcing The MT55L256L18P1F-10 is listed as Active in production — no end-of-life notice, no last-time-buy pressure. It is RoHS non-compliant (per the listing), so verify your assembly house's exemption policy if you need lead-free solder. This part is sourced and quoted to order through independent distribution; availability and current pricing are confirmed at quote time. For volume BOM commitments, an RFQ is the right next step.","metaTitle":"Micron MT55L256L18P1F-10 ZBT SRAM, 4Mbit, 5 ns, 100 MHz","metaDescription":"Micron MT55L256L18P1F-10 ZBT SRAM, 4Mbit (256K x 18), 5 ns access, 100 MHz clock, 165-FBGA, commercial temp. Active, sourced to order.","metaKeywords":null},"attributes":{"series":"ZBT®","packageCase":null,"mountingType":null,"rohsStatus":"RoHS non-compliant","productStatus":"Active","categoryPath":["Microcontrollers & Processors (MCU / MPU / DSP)"],"specifications":{"Series":"ZBT®","Package":"Bulk","Technology":"SRAM - ZBT","Access Time":"5 ns","Memory Size":"4Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-TBGA","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.465V","Memory Organization":"256K x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (13x15)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$5.51","stockQuantity":0,"priceTiers":[{"qty":55,"price":"$5.51000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/c933e0ca964e8883e349e54cdea584ba.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is MT55L256L18P1F-10 obsolete or end-of-life?","answer":"No, the MT55L256L18P1F-10 is listed as Active in production. There is no end-of-life notice or last-time-buy window currently in effect."},{"question":"What is the access time of MT55L256L18P1F-10?","answer":"The access time is 5 ns, which allows single-cycle read/write at the rated 100 MHz clock."},{"question":"Is MT55L256L18P1F-10 RoHS compliant?","answer":"No, the MT55L256L18P1F-10 is listed as RoHS non-compliant. Check your assembly house's exemption policy if lead-free solder is required."},{"question":"What is the exact package and pinout of MT55L256L18P1F-10?","answer":"The package is a 165-ball TBGA (13x15 mm body), surface-mount only. The pinout is defined by the Micron ZBT SRAM family standard; consult the device datasheet for the ball-map diagram."},{"question":"Does MT55L256L18P1F-10 require any special programming or configuration?","answer":"No special programming is required. It is a standard synchronous SRAM with a parallel interface; configuration is handled entirely by the memory controller at power-up."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/micron/MT55L256L18P1F-10","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/micron/MT55L256L18P1F-10 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-11T19:21:25.372Z","lastPublished":"2026-07-11T19:21:25.372Z","indexable":true}}