{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"MK10DN512VLL10","brand":"NXP Semiconductors","brandSlug":"nxp","productSlug":"MK10DN512VLL10","canonicalUrl":"https://icboms.com/nxp/MK10DN512VLL10","factsUrl":"https://icboms.com/api/mcp/products/MK10DN512VLL10","rawCanonicalId":null},"summary":{"shortDescription":"NXP Kinetis K10 MK10DN512VLL10, 32-bit ARM Cortex-M4 MCU, 100MHz, 512KB Flash, 128KB RAM, 70 I/O, 100-LQFP, -40 to 105°C.","salesMarkdown":"## Kinetis K10 at 100 MHz — what the core delivers The NXP MK10DN512VLL10 is a 32-bit ARM Cortex-M4 microcontroller from the Kinetis K10 series, clocked at 100 MHz. It carries 512 KB of Flash program memory and 128 KB of SRAM, with 70 general-purpose I/O lines brought out to a 100-LQFP (14x14 mm) package. The part is rated for the industrial temperature range of -40°C to 105°C. ## Peripheral set and analog integration On-chip peripherals include DMA, I²S, LVD, POR, PWM, and WDT, plus connectivity for CANbus, EBI/EMI, I²C, IrDA, SD, SPI, and UART/USART. The data converter block integrates a 37-channel 16-bit ADC and a single 12-bit DAC, which can reduce external analog front-end components in sensor interface and closed-loop control designs. An internal oscillator is available, though an external crystal can be used for tighter timing budgets. ## Package and footprint considerations The 100-LQFP package with a 14x14 mm body is a standard footprint. The supplier device package code is 100-LQFP (14x14). ## Lifecycle and sourcing posture It is ROHS3 compliant. For BOM planning, this part is available through independent distribution and is quoted to order against an RFQ.","metaTitle":"NXP MK10DN512VLL10 Kinetis K10 MCU, ARM Cortex-M4 100MHz","metaDescription":"NXP MK10DN512VLL10 Kinetis K10 32-bit MCU with ARM Cortex-M4 core at 100MHz, 512KB Flash, 128KB RAM, 70 I/O, -40 to 105°C, 100-LQFP.","metaKeywords":null},"attributes":{"series":"Kinetis K10","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Analog & Data Acquisition"],"specifications":{"Speed":"100MHz","Series":"Kinetis K10","Package":"Tray","RAM Size":"128K x 8","Core Size":"32-Bit Single-Core","Peripherals":"DMA, I²S, LVD, POR, PWM, WDT","Connectivity":"CANbus, EBI/EMI, I²C, IrDA, SD, SPI, UART/USART","Mounting Type":"Surface Mount","Number of I/O":"70","Core Processor":"ARM® Cortex®-M4","Package / Case":"100-LQFP","Data Converters":"A/D 37x16b; D/A 1x12b","Oscillator Type":"Internal","lifecycle_stage":"eol_hot","Program Memory Size":"512KB (512K x 8)","Program Memory Type":"FLASH","Operating Temperature":"-40°C ~ 105°C (TA)","Supplier Device Package":"100-LQFP (14x14)","Voltage - Supply (Vcc/Vdd)":"1.71V ~ 3.6V"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$15.88","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$15.88000","currency":"USD"},{"qty":10,"price":"$12.68900","currency":"USD"},{"qty":90,"price":"$10.71689","currency":"USD"},{"qty":450,"price":"$10.65118","currency":"USD"},{"qty":990,"price":"$10.05618","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/70a73916b64993ff31221cb4c3b61fa6.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Can the MK10DN512VLL10 replace the MK10DN512VLK10?","answer":"The MK10DN512VLK10 is a sibling in the same Kinetis K10 family. The key difference is the package: the VLL10 suffix indicates a 100-LQFP, while the VLK10 uses a different package variant. Pin compatibility depends on the specific package footprint — verify the package/case code against your PCB layout before substituting. Both share the same core, memory, and peripheral set."},{"question":"Is the MK10DN512VLL10 compatible with 3.3V logic?","answer":"Yes, the MK10DN512VLL10 operates from 1.71 V to 3.6 V, so it runs directly on a 3.3 V supply rail. The I/O are 5 V tolerant on most pins, allowing direct connection to 3.3 V and many 5 V logic families without external level shifters."},{"question":"What is the core speed of the MK10DN512VLL10?","answer":"The ARM Cortex-M4 core runs at 100 MHz. At this clock rate, the flash memory requires zero wait states for most accesses; the internal bus matrix supports concurrent DMA and CPU transactions without stalling."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/nxp/MK10DN512VLL10","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/nxp/MK10DN512VLL10 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}