{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"MCP48FEB28-E/MQ","brand":"Microchip Technology","brandSlug":"microchip","productSlug":"MCP48FEB28-E-MQ","canonicalUrl":"https://icboms.com/microchip/MCP48FEB28-E-MQ","factsUrl":"https://icboms.com/api/mcp/products/MCP48FEB28-E%2FMQ","rawCanonicalId":null},"summary":{"shortDescription":"Microchip MCP48FEB28-E/MQ, Automotive AEC-Q100, 12-bit quad DAC, SPI, voltage-unbuffered output, 7.8 µs settling, ±0.4 LSB INL, -40°C to 125°C, 20-VQFN exposed pad.","salesMarkdown":"The MCP48FEB28-E/MQ is a 12-bit, quad-channel DAC from Microchip, part of the Automotive AEC-Q100 series. It integrates four independent voltage-output DACs with an SPI interface, each settling to 0.5 LSB in 7.8 µs typical — fast enough for real-time trim and set-point updates in automotive actuator loops or industrial closed-loop control. The 7.8 µs settling time means each channel can update at roughly 128 kHz before the output has not settled to within 0.5 LSB of the final value. For a multi-channel system sequencing four DACs over one SPI bus, the aggregate throughput is bus-limited — the SPI clock rate and the 16-bit frame per channel set the actual update rate, not the DAC settling alone. ## INL and DNL — monotonicity over temperature Integral nonlinearity is ±0.4 LSB maximum, and differential nonlinearity is ±0.05 LSB maximum across the full -40°C to 125°C range. The DNL spec guarantees monotonicity — every increase in digital code produces a positive output step, which is essential for closed-loop control where a non-monotonic DAC would cause the loop to reverse direction. ## Supply range and reference — single-rail simplicity The reference is external — the designer picks the reference voltage that sets the output span, which decouples the DAC accuracy from the supply tolerance. An unbuffered voltage output means the DAC output impedance is code-dependent; the load impedance must be high enough (typically >10 kΩ) to keep the voltage error below 1 LSB. ## Package and footprint — 20-VQFN with exposed pad The 0.65 mm pitch is manageable on a two-layer board with careful fan-out.","metaTitle":"MCP48FEB28-E/MQ 12-bit quad DAC, SPI, AEC-Q100","metaDescription":"Microchip MCP48FEB28-E/MQ: 12-bit quad DAC, SPI interface, ±0.4 LSB INL, 7.8 µs settling, -40°C to 125°C, AEC-Q100.","metaKeywords":null},"attributes":{"series":"Automotive, AEC-Q100","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Discrete Semiconductors"],"specifications":{"Series":"Automotive, AEC-Q100","Package":"Tube","Output Type":"Voltage - Unbuffered","INL/DNL (LSB)":"±0.4LSB, ±0.05LSB","Mounting Type":"Surface Mount","Settling Time":"7.8µs (Typ)","Data Interface":"SPI","Number of Bits":"12","Package / Case":"20-VQFN Exposed Pad","Reference Type":"External","lifecycle_stage":"eol_hot","Differential Output":"No","Operating Temperature":"-40°C ~ 125°C","Supplier Device Package":"20-VQFN (5x5)","Number of D/A Converters":"4","Voltage - Supply, Analog":"2.7V ~ 5.5V","Voltage - Supply, Digital":"2.7V ~ 5.5V"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$12.26","priceTiers":[{"qty":1,"price":"$12.26000","currency":"USD"},{"qty":25,"price":"$10.21840","currency":"USD"},{"qty":100,"price":"$9.45000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/93c9abd4cf38fdf2ec1c2837a6a3415b.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/MCP48FEB28-E%2FMQ/alternatives.json"},"ai":{"faq":[{"question":"What is the difference between MCP48FEB28 and MCP48FEB22?","answer":"The MCP48FEB28 has four DAC channels; the MCP48FEB22 has two. Both are 12-bit, SPI, AEC-Q100 qualified, and share the same 20-VQFN package footprint. The channel count is the only parametric difference — the two-channel variant is a cost-optimised option when fewer analog outputs are needed."},{"question":"Does MCP48FEB28-E/MQ support SPI mode 0?","answer":"The SPI interface on this DAC supports modes 0,0 and 1,1 — clock polarity (CPOL) = 0 or 1 with clock phase (CPHA) = 0. Mode 0 (CPOL=0, CPHA=0) is the most common and is supported. The input data is clocked in on the rising edge of SCK in mode 0."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/microchip/MCP48FEB28-E-MQ","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/microchip/MCP48FEB28-E-MQ when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}