{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"M5M5V108DKV-70HIST","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"M5M5V108DKV-70HIST","canonicalUrl":"https://icboms.com/renesas/M5M5V108DKV-70HIST","factsUrl":"https://icboms.com/api/mcp/products/M5M5V108DKV-70HIST","rawCanonicalId":null},"summary":{"shortDescription":"Mitsubishi M5M5V108DKV-70HIST, Standard SRAM, 128Kx8, 70 ns access time, CMOS, Bulk package.","salesMarkdown":"## 128K x 8 SRAM with 70 ns access — bus timing and memory map The M5M5V108DKV-70HIST is a 128K x 8 standard SRAM from Mitsubishi, organized as 128K words of 8 bits each, with a 70 ns access time. The 70 ns rating governs the read/write cycle timing on the bus — a 70 ns access means the data is valid 70 ns after the address is presented, which sets the minimum wait-state requirement for the memory controller. The 128K x 8 organization maps directly to an 8-bit data bus and provides 128 KB of volatile storage, suitable for code scratchpad, data buffering, or lookup tables in embedded systems. ## Active lifecycle — no obsolescence risk for new designs For a BOM freeze or a production line that needs a stable SRAM supply, this part presents no near-term obsolescence risk.","metaTitle":"M5M5V108DKV-70HIST 128Kx8 SRAM, 70 ns, Active","metaDescription":"Mitsubishi SRAM, 128Kx8 organization, 70 ns access time. Active lifecycle, bulk packaging.","metaKeywords":null},"attributes":{"series":"*","packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Analog & Data Acquisition"],"specifications":{"Series":"*","Package":"Bulk","lifecycle_stage":"eol_hot"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$5.05","stockQuantity":0,"priceTiers":[{"qty":60,"price":"$5.05000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/6f5abb276108f59b98d5e4d67fa85d62.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the access time of M5M5V108DKV-70HIST?","answer":"The access time is 70 ns, which defines the maximum time from address assertion to valid data output on the bus."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/M5M5V108DKV-70HIST","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/M5M5V108DKV-70HIST when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}