{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"M24C64-WMN6P","brand":"STMicroelectronics","brandSlug":"stmicroelectronics","productSlug":"M24C64-WMN6P","canonicalUrl":"https://icboms.com/stmicroelectronics/M24C64-WMN6P","factsUrl":"https://icboms.com/api/mcp/products/M24C64-WMN6P","rawCanonicalId":null},"summary":{"shortDescription":"STMicroelectronics M24C64 I2C EEPROM, 64Kbit (8K × 8), 2.5–5.5 V supply, 1 MHz clock, 450 ns access, 5 ms write cycle, 8-SOIC (Tube), -40°C to 85°C.","salesMarkdown":"## 64 Kbit I2C EEPROM — what the 450 ns access and 1 MHz bus clock mean for your design The STMicroelectronics M24C64-WMN6P is a 64 Kbit serial EEPROM organized as 8K x 8 bits, accessed over an I2C bus at up to 1 MHz. The 450 ns access time is the random-read cycle — the time from the address byte to the first data byte appearing on SDA. For a host controller polling the bus, that 450 ns window sets the minimum SCL high time before sampling; the part itself does not stretch the clock, so the master must hold SCL stable for the full access window or risk reading stale data. The 5 ms write cycle time is the page-write duration — the bus is held busy during that interval, so the host must either poll the acknowledge polling sequence or insert a delay before the next write. ## NRND — not for new designs, but still a valid BOM line for existing production That means STMicroelectronics still manufactures it for existing customers, but no new design-ins should target this order code. For a production BOM already qualified on this part, the NRND flag is a signal to plan a migration — not an immediate crisis. ## 8-SOIC package — rework-friendly footprint for hand assembly or reflow The lead pitch is 1.27 mm — wide enough for a standard chisel tip or hot-air nozzle without bridging. The body sits low enough that underfill is not required for typical industrial temperature cycling.","metaTitle":"STMicroelectronics M24C64-WMN6P I2C EEPROM, 64Kbit, 1 MHz","metaDescription":"STMicroelectronics M24C64-WMN6P 64Kbit I2C EEPROM, 1 MHz clock, 450 ns access, 2.5-5.5 V supply, -40 to 85°C, 8-SOIC.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"NRND","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"STMicroelectronics","Series":"-","Package":"Tube","Technology":"EEPROM","Access Time":"450 ns","Memory Size":"64Kbit","Memory Type":"Non-Volatile","Memory Format":"EEPROM","Mounting Type":"Surface Mount","Package / Case":"8-SOIC (0.154\\\", 3.90mm Width)","Product Status":"Not For New Designs","Clock Frequency":"1 MHz","lifecycle_stage":"eol_hot","Memory Interface":"I²C","Voltage - Supply":"2.5V ~ 5.5V","Base Product Number":"M24C64","Memory Organization":"8K x 8","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"8-SOIC","Write Cycle Time - Word, Page":"5ms"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$0.3000","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/f80a2f163f84bd6e64a778a5e4f1c6d9.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/M24C64-WMN6P/alternatives.json"},"ai":{"faq":[{"question":"Is the M24C64-WMN6P recommended for new designs?","answer":"It is still available for existing production BOMs, but new designs should target an active M24C64 variant in the same 8-SOIC footprint."},{"question":"What is the difference between M24C64-WMN6P and M24C64-WMN6T?","answer":"The M24C64-WMN6P ships in Tube packaging; the M24C64-WMN6T ships in Tape & Reel. Both are the same die, same 8-SOIC package, same electrical specifications — the only difference is the shipping medium. The WMN6T is typically used for automated pick-and-place assembly lines."},{"question":"What is the maximum operating frequency of M24C64-WMN6P?","answer":"The I2C bus clock runs at up to 1 MHz. The random-read access time is 450 ns, which the master must respect by holding SCL stable during the read cycle."},{"question":"What is the write cycle time of the M24C64-WMN6P?","answer":"The write cycle time — word or page — is 5 ms. During this interval the bus is held busy; the host must either poll the acknowledge polling sequence or insert a 5 ms delay before the next write command."},{"question":"Is M24C64-WMN6P compatible with 3.3V logic?","answer":"The I2C bus thresholds are proportional to VCC, so at 3.3 V supply the logic levels are fully compatible with 3.3 V microcontrollers."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/stmicroelectronics/M24C64-WMN6P","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/stmicroelectronics/M24C64-WMN6P when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-16T10:39:33.080Z","lastPublished":"2026-07-16T10:39:33.080Z","indexable":true}}