{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"LS1012AXE7EKA","brand":"NXP Semiconductors","brandSlug":"nxp","productSlug":"LS1012AXE7EKA","canonicalUrl":"https://icboms.com/nxp/LS1012AXE7EKA","factsUrl":"https://icboms.com/api/mcp/products/LS1012AXE7EKA","rawCanonicalId":null},"summary":{"shortDescription":"NXP QorIQ® Layerscape LS1012AXE7EKA, single-core 64-bit ARM® Cortex®-A53 MPU, 600 MHz, USB 2.0 (1) + USB 3.0 with integrated PHY, SATA 6 Gbps (1), dual GbE, DDR3L controller, Secure Boot & TrustZone, -40°C to 105°C, 211-FCLGA (9.6x9.6 mm), tray.","salesMarkdown":"## What this 600 MHz single-core A53 MPU is for The NXP LS1012AXE7EKA is a single-core 64-bit ARM Cortex-A53 microprocessor from the QorIQ Layerscape family, clocked at 600 MHz. It targets power-sensitive networking, IoT gateway, and industrial control applications where a full application processor is needed but the thermal and cost budget won't stretch to a multi-core part. The single A53 core with 64-bit datapath gives it enough headroom for a Linux control plane or a lightweight data-forwarding stack while keeping the power draw low enough for fanless enclosures. ## I/O mix: USB 3.0 + PHY, SATA 6 Gbps, dual GbE The integrated USB 3.0 port includes the PHY on-chip, saving a separate transceiver and the associated BOM cost. A second USB 2.0 port is available for lower-speed peripherals or debug. The single SATA 6 Gbps channel lets you attach an SSD or HDD directly for local storage — useful for an edge gateway that buffers sensor data. Two Gigabit Ethernet MACs are present; the buyer should verify whether the external PHY interface is RGMII or SGMII in the full datasheet, as that affects the PHY selection and PCB trace routing. The 211-FCLGA package measures 9.6x9.6 mm — a land-grid array, not a BGA, so there are no solder balls to collapse during reflow. The LGA footprint is more forgiving for hand-assembly and rework, but the pad layout and stencil aperture still need careful design to avoid voids under the large central ground pad. Surface-mount only. ## Security features: Secure Boot and TrustZone Secure Boot and TrustZone are listed as security features. Secure Boot ensures only authenticated firmware executes from power-on, which is a hard requirement for any device that connects to the internet or a corporate network. TrustZone provides a hardware-isolated trusted execution environment for cryptographic keys and secure firmware updates. If your design needs to pass PSA Certified Level 1 or similar, this part covers the baseline hardware root of trust without an external secure element. ## Lifecycle and supply posture ROHS3 compliant.","metaTitle":"NXP LS1012AXE7EKA QorIQ Layerscape MPU","metaDescription":"NXP LS1012AXE7EKA QorIQ Layerscape single-core 64-bit ARM Cortex-A53 MPU at 600 MHz. USB 3.0 + PHY, SATA 6 Gbps, dual GbE. Industrial temp -40°C to 105°C.","metaKeywords":null},"attributes":{"series":"QorIQ® Layerscape","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Logic ICs"],"specifications":{"USB":"USB 2.0 (1), USB 3.0 + PHY","SATA":"SATA 6Gbps (1)","Speed":"600MHz","Series":"QorIQ® Layerscape","Package":"Tray","Ethernet":"GbE (2)","Mounting Type":"Surface Mount","Core Processor":"ARM® Cortex®-A53","Package / Case":"211-VFLGA","RAM Controllers":"DDR3L","lifecycle_stage":"eol_hot","Security Features":"Secure Boot, TrustZone®","Operating Temperature":"-40°C ~ 105°C","Supplier Device Package":"211-FCLGA (9.6x9.6)","Number of Cores/Bus Width":"1 Core, 64-Bit"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$38.67","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$38.67000","currency":"USD"},{"qty":10,"price":"$31.01000","currency":"USD"},{"qty":168,"price":"$26.48006","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/8cc09550cd042f064ada98dff138f994.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What interfaces does LS1012AXE7EKA integrate?","answer":"It integrates one USB 3.0 port with integrated PHY, one USB 2.0 port, one SATA 6 Gbps channel, and two Gigabit Ethernet MACs. A DDR3L memory controller is also on-chip."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/nxp/LS1012AXE7EKA","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/nxp/LS1012AXE7EKA when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}