{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"LS1012ASE7EKA","brand":"NXP Semiconductors","brandSlug":"nxp","productSlug":"LS1012ASE7EKA","canonicalUrl":"https://icboms.com/nxp/LS1012ASE7EKA","factsUrl":"https://icboms.com/api/mcp/products/LS1012ASE7EKA","rawCanonicalId":null},"summary":{"shortDescription":"NXP QorIQ® Layerscape LS1012ASE7EKA, single-core ARM® Cortex®-A53 64-bit MPU at 600 MHz, USB 2.0 (1) + USB 3.0 with PHY, SATA 6Gbps (1), dual GbE, DDR3L, Secure Boot and TrustZone, 211-FCLGA (9.6x9.6 mm), 0 to 105 °C, tray.","salesMarkdown":"## I/O complement: USB 3.0, SATA 6Gbps, dual GbE This MPU carries one USB 3.0 port with integrated PHY, one SATA 6 Gbps port, and two Gigabit Ethernet MACs. The USB 3.0 + PHY saves an external transceiver; the SATA port connects directly to a storage drive or SSD. The dual GbE ports support bridging or a WAN/LAN split in a gateway design. One USB 2.0 port is also present for lower-speed peripherals. ## Memory interface: DDR3L only The RAM controller is specified for DDR3L only — no DDR4 or LPDDR4 support. If your BOM calls for DDR3L, this part fits; if the design targets DDR4, this is the wrong memory interface. The single-channel DDR3L controller is adequate for the single-core's bandwidth needs in the target applications. ## Package and assembly: 211-FCLGA, 9.6x9.6 mm The LS1012ASE7EKA comes in a 211-ball FCLGA package, 9.6 mm square. It is a surface-mount LGA — no balls to reflow, just a land-grid array. The tray shipping medium is what you get; this variant is not offered in tape and reel. The small footprint suits space-constrained designs, but the LGA package requires a solder-paste stencil and reflow profile tuned for leadless packages. ## Temperature grade: 0 to 105 °C Rated for 0 °C to 105 °C operating junction temperature. ## Security features: Secure Boot and TrustZone Hardware security includes Secure Boot and ARM TrustZone. Secure Boot verifies the bootloader signature before execution; TrustZone creates a trusted execution environment for cryptographic keys and secure firmware updates. These are standard for IoT edge nodes and gateway products that need to resist firmware tampering. ## Lifecycle and sourcing No end-of-life notice or last-time-buy window is in effect. This is a current, catalogued part available through the independent distribution channel.","metaTitle":"NXP LS1012ASE7EKA QorIQ Layerscape MPU, 600 MHz, 211-FCLGA","metaDescription":"NXP LS1012ASE7EKA QorIQ Layerscape single-core ARM Cortex-A53 MPU at 600 MHz. USB 3.0, SATA 6Gbps, dual GbE. DDR3L, Secure Boot, TrustZone. 0 to 105 °C.","metaKeywords":null},"attributes":{"series":"QorIQ® Layerscape","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["DC-DC Power Modules"],"specifications":{"USB":"USB 2.0 (1), USB 3.0 + PHY","SATA":"SATA 6Gbps (1)","Speed":"600MHz","Series":"QorIQ® Layerscape","Package":"Tray","Ethernet":"GbE (2)","Mounting Type":"Surface Mount","Core Processor":"ARM® Cortex®-A53","Package / Case":"211-VFLGA","RAM Controllers":"DDR3L","lifecycle_stage":"eol_hot","Security Features":"Secure Boot, TrustZone®","Operating Temperature":"0°C ~ 105°C","Supplier Device Package":"211-FCLGA (9.6x9.6)","Number of Cores/Bus Width":"1 Core, 64-Bit"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$35.13","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$35.13000","currency":"USD"},{"qty":10,"price":"$28.17600","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/8cc09550cd042f064ada98dff138f994.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is LS1012ASE7EKA compatible with DDR3L?","answer":"Yes, the RAM controller is specified for DDR3L. DDR4 and LPDDR4 are not supported on this part."},{"question":"Does LS1012ASE7EKA have secure boot and TrustZone?","answer":"Yes, it includes Secure Boot and ARM TrustZone hardware security features for verified boot and trusted execution."},{"question":"What is the difference between LS1012ASE7EKA and LS1012AXE7EKA?","answer":"The LS1012AXE7EKA is a different speed-grade or feature-set variant within the same LS1012 family. The 'SE7' suffix on this part indicates the 600 MHz speed grade. Pin compatibility across the LS1012 family should be verified against the NXP datasheet for the specific package and feature set."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/nxp/LS1012ASE7EKA","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/nxp/LS1012ASE7EKA when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-13T22:23:18.678Z","lastPublished":"2026-07-13T22:23:18.678Z","indexable":true}}