{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"LPC11U37HFBD64/401151","brand":"NXP USA Inc.","brandSlug":"nxp-usa-inc","productSlug":"LPC11U37HFBD64-401151","canonicalUrl":"https://icboms.com/nxp-usa-inc/LPC11U37HFBD64-401151","factsUrl":"https://icboms.com/api/mcp/products/LPC11U37HFBD64%2F401151","rawCanonicalId":null},"summary":{"shortDescription":"NXP LPC11U37HFBD64/401151, ARM Cortex-M0 32-bit MCU, 50 MHz, 128 KB Flash, 10 KB RAM, 4 KB EEPROM, USB 2.0 device, I²C/SPI/UART, 54 I/O, 1.8–3.6 V, -40 to 85 °C, 64-LQFP.","salesMarkdown":"## 50 MHz core — timing headroom for USB and control loops The 50 MHz Cortex-M0 core delivers enough throughput to handle USB interrupt transfers alongside a moderate control loop or a Modbus RTU stack without stalling. For designs that need more deterministic response, the DMA controller listed in the peripheral set can offload peripheral-to-memory transfers. The 10 KB RAM is tight for large buffers; plan the USB endpoint descriptor and packet buffers within that footprint. ## Memory map — 128 KB Flash, 4 KB EEPROM The 128 KB Flash holds firmware and constant tables. The 4 KB EEPROM is a separate nonvolatile block rated for parameter calibration data, configuration bytes, or last-state retention — no external serial EEPROM needed for small datasets. The 10 KB SRAM must cover stack, heap, and runtime variables; watch the linker map if the application uses USB with multiple endpoints. It is available for BOM insertion into new designs without LTB risk.","metaTitle":"NXP LPC11U37HFBD64/401151 ARM Cortex-M0 MCU, 50 MHz","metaDescription":"NXP LPC11U37HFBD64/401151 ARM Cortex-M0 MCU, 50 MHz, 128 KB Flash, 10 KB RAM, 4 KB EEPROM, USB, -40 to 85°C, 64-LQFP. Active production, available to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Microcontrollers & Processors (MCU / MPU / DSP)"],"specifications":{"Mfr":"NXP USA Inc.","Speed":"50MHz","Series":"LPC11Uxx","Package":"Bulk","RAM Size":"10K x 8","Core Size":"32-Bit Single-Core","EEPROM Size":"4K x 8","Peripherals":"Brown-out Detect/Reset, DMA, POR, PWM, WDT","Connectivity":"I²C, Microwire, SmartCard, SPI, SSP, UART/USART, USB","Mounting Type":"Surface Mount","Number of I/O":"54","Core Processor":"ARM® Cortex®-M0","Package / Case":"64-LQFP","Product Status":"Active","Data Converters":"A/D 8x10b","Oscillator Type":"Internal","lifecycle_stage":"unknown","Base Product Number":"LPC11","Program Memory Size":"128KB (128K x 8)","Program Memory Type":"FLASH","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"64-LQFP (10x10)","Voltage - Supply (Vcc/Vdd)":"1.8V ~ 3.6V"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/8659c114783192eafc40b6b71a313f58.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/LPC11U37HFBD64%2F401151/alternatives.json"},"ai":{"faq":[{"question":"What is the closest pin-compatible alternative to LPC11U37HFBD64/401151 in this family?","answer":"Within the LPC11Uxx series, pin-compatible variants differ mainly in Flash and RAM density. The LPC11U37HFBD64/401151 sits at the 128 KB Flash / 10 KB RAM tier; lower-density siblings (e.g., 64 KB Flash) share the same 64-LQFP footprint and peripheral set, allowing a drop-in BOM adjustment without a board spin."},{"question":"What is LPC11U37HFBD64/401151's listed speed?","answer":"The core is rated at 50 MHz, which is the maximum CPU clock for this Cortex-M0 device."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/nxp-usa-inc/LPC11U37HFBD64-401151","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/nxp-usa-inc/LPC11U37HFBD64-401151 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-11T17:20:20.394Z","lastPublished":"2026-07-11T17:20:20.394Z","indexable":true}}