{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"LMK03328RHST","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"LMK03328RHST","canonicalUrl":"https://icboms.com/texas-instruments/LMK03328RHST","factsUrl":"https://icboms.com/api/mcp/products/LMK03328RHST","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments LMK03328RHST clock generator, PLL with bypass, 1 GHz max frequency, 2:8 input-output, LVCMOS input, CML/HCSL/LVCMOS/LVDS/LVPECL outputs, 48-WFQFN exposed pad, active.","salesMarkdown":"## 1 GHz clock synthesis — output flexibility The LMK03328RHST: The PLL core generates up to 1 GHz on the outputs, covering the reference clock rates for most high-speed SerDes, FPGA transceivers, and Ethernet PHYs. The 2:8 input-to-output ratio means two reference inputs feed eight synthesised outputs — enough to distribute a clean clock to multiple ASICs or line cards without external fan-out buffers. Output format is configurable across CML, HCSL, LVCMOS, LVDS, and LVPECL. A single device can drive a PCIe reference (HCSL), a backplane clock (LVDS), and a local FPGA fabric clock (LVCMOS) from the same die, reducing the component count in a mixed-signal timing tree. The PLL includes a bypass mode, which lets the input clock pass through to the outputs without phase-locked-loop processing. This is useful for jitter-sensitive paths where the PLL's own phase noise would degrade the signal, or for test modes where a clean reference is needed directly. ## Supply and temperature — board-level fit The wide range also allows the same BOM to serve multiple voltage domains across different board spins.","metaTitle":"TI LMK03328RHST Clock Generator, 1 GHz, Active","metaDescription":"Texas Instruments LMK03328RHST clock generator with PLL bypass, 1 GHz max frequency, 2:8 input-output ratio, LVCMOS input, CML/HCSL/LVDS/LVPECL outputs.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"Mfr":"Texas Instruments","PLL":"Yes with Bypass","Input":"LVCMOS","Output":"CML, HCSL, LVCMOS, LVDS, LVPECL","Series":"-","Package":"Tape & Reel (TR); Cut Tape (CT)","Mounting Type":"Surface Mount","Package / Case":"48-WFQFN Exposed Pad","Product Status":"Active","Frequency - Max":"1GHz","lifecycle_stage":"eol_hot","Voltage - Supply":"1.7V ~ 3.465V","Divider/Multiplier":"Yes/Yes","Number of Circuits":"1","Base Product Number":"LMK03328","Ratio - Input:Output":"2:8","Operating Temperature":"-40°C~85°C","Supplier Device Package":"48-WQFN (7x7)","Differential - Input:Output":"Yes/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$21.9800","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/9f92d4dbf4600cd74c2fdae88ceec14a.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/LMK03328RHST/alternatives.json"},"ai":{"faq":[{"question":"What is LMK03328RHST's maximum output frequency?","answer":"The device supports a maximum output frequency of 1 GHz. This ceiling applies to the differential outputs (CML, HCSL, LVDS, LVPECL); the LVCMOS output is typically limited to lower rates by the single-ended drive capability."},{"question":"What output standards does the LMK03328RHST support?","answer":"It can be configured for CML, HCSL, LVCMOS, LVDS, or LVPECL outputs. This covers the common high-speed serial interface standards used in PCIe, Ethernet, and FPGA transceiver reference clocks."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/LMK03328RHST","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/LMK03328RHST when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}