{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"LMK00105SQX/NOPB","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"LMK00105SQX-NOPB","canonicalUrl":"https://icboms.com/texas-instruments/LMK00105SQX-NOPB","factsUrl":"https://icboms.com/api/mcp/products/LMK00105SQX%2FNOPB","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments LMK00105SQX/NOPB Fanout Buffer (Distribution), Multiplexer, Translator, 200 MHz max, 2:5 ratio, 24-WFQFN Exposed Pad, Tape & Reel.","salesMarkdown":"## What this clock buffer does on the board The LMK00105SQX/NOPB is a three-in-one clock-tree part: a fanout buffer, a signal multiplexer, and a level translator in a single 24-WQFN package. It takes in one of seven differential or single-ended input formats — HCSL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, or a crystal — and outputs five copies of that clock in LVCMOS logic levels. The 2:5 input-to-output ratio means you can select between two clock sources (the mux function) and distribute the chosen clock to five downstream loads without adding a separate mux and fanout buffer. The differential inputs accept a clean differential clock while the single-ended outputs drive standard CMOS logic — no external level-shifting resistors needed between the clock source and the FPGA or ASIC bank. ## Frequency ceiling and signal integrity Rated to 200 MHz maximum, this buffer handles the common clock rates for Gigabit Ethernet, PCIe Gen 1/2 reference clocks, and most FPGA fabric clocks. The differential input path preserves signal integrity at the higher end of the band — the HCSL or LVDS inputs reject common-mode noise picked up on the board trace between the oscillator and this buffer. ## Package reality for the rework bench Will it survive hot air? Yes — the QFN body is small enough that a preheat plate at 150 °C followed by a hot-air nozzle at 300 °C lifts the part cleanly without lifting adjacent passives, as long as the board has adequate copper soak under the pad. The 24-WQFN (4x4) supplier device package matches the industry-standard QFN footprint, so replacement parts from the same reel reflow back without pad realignment. ## Active lifecycle and procurement posture The base product number LMK00105 covers the whole family; the /NOPB suffix indicates lead-free (RoHS-compliant) plating on the terminations.","metaTitle":"LMK00105SQX/NOPB Fanout Buffer, 200 MHz, 24-WQFN","metaDescription":"TI LMK00105SQX/NOPB active fanout buffer, 200 MHz max, 2:5 ratio, accepts HCSL/LVDS/LVPECL/Crystal inputs. 24-WQFN package. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"Mfr":"Texas Instruments","Type":"Fanout Buffer (Distribution), Multiplexer, Translator","Input":"HCSL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, Crystal","Output":"LVCMOS","Series":"-","Package":"Tape & Reel (TR)","Mounting Type":"Surface Mount","Package / Case":"24-WFQFN Exposed Pad","Product Status":"Active","Frequency - Max":"200 MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"2.375V ~ 3.45V","Number of Circuits":"1","Base Product Number":"LMK00105","Ratio - Input:Output":"2:5","Operating Temperature":"-40°C~85°C","Supplier Device Package":"24-WQFN (4x4)","Differential - Input:Output":"Yes/No"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$3.1185","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/b61b2baef3a087ee8f1c9a99af1fe74d.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/LMK00105SQX%2FNOPB/alternatives.json"},"ai":{"faq":[{"question":"What input formats does this clock buffer accept?","answer":"It accepts HCSL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, and crystal inputs — seven signal types covering differential and single-ended clock sources. The differential input path (HCSL, LVDS, LVPECL) is the preferred route for low-jitter clock distribution above 100 MHz."},{"question":"What is the maximum frequency this part can buffer?","answer":"200 MHz maximum. This covers reference clocks for Gigabit Ethernet, PCIe Gen 1/2, SATA, and most FPGA fabric PLL reference inputs."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/LMK00105SQX-NOPB","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/LMK00105SQX-NOPB when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}