{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"HMC7044LP10BETR","brand":"Analog Devices","brandSlug":"analog-devices","productSlug":"HMC7044LP10BETR","canonicalUrl":"https://icboms.com/analog-devices/HMC7044LP10BETR","factsUrl":"https://icboms.com/api/mcp/products/HMC7044LP10BETR","rawCanonicalId":null},"summary":{"shortDescription":"Analog Devices HMC7044LP10BETR jitter attenuator, PLL Yes, Type Jitter Attenuator, Input CML/CMOS/LVDS/LVPECL, Output CML/LVDS/LVPECL, Frequency - Max 3.2GHz, 68-VFQFN Exposed Pad CSP, -40°C to 85°C.","salesMarkdown":"## PLL-based jitter attenuator for 3.2 GHz clock cleaning The Analog Devices HMC7044LP10BETR is a PLL-based jitter attenuator designed to clean and distribute high-frequency reference clocks in communications and data-converter systems. It accepts CML, CMOS, LVDS, or LVPECL inputs and provides the same output logic family options, so no external level translation is needed between the reference source and the downstream ADC, DAC, or FPGA. The 4:14 input-to-output ratio lets a single clean reference fan out to multiple clock domains — useful when a base station or test equipment board has several ASICs each requiring a low-jitter clock. Maximum output frequency of 3.2 GHz covers the upper range of JESD204B and high-speed serial interfaces. The single PLL core locks to the input reference and attenuates phase noise from the source, delivering a cleaned clock to the outputs. For a clock-cleaning application, the PLL bandwidth is set by external loop-filter components — the datasheet layout gives recommended values for typical loop bandwidths. ## Supply, temperature, and package — what they mean on the board All inputs and outputs are differential, which helps reject common-mode noise picked up on long clock traces between boards. The single-circuit PLL means one reference input, one cleaned output bank — not a multi-PLL synthesizer. If your application needs independent clock domains from different references, consider a multi-PLL clock generator instead. ## Lifecycle and sourcing — active, no obsolescence risk For new designs, this part can be specified without worrying about a near-term phase-out.","metaTitle":"HMC7044LP10BETR Jitter Attenuator, 3.2 GHz, PLL, 68-LFCSP","metaDescription":"Analog Devices HMC7044LP10BETR jitter attenuator IC with PLL, 3.2 GHz max frequency, 4:14 I/O ratio, CML/CMOS/LVDS/LVPECL. Industrial temp -40°C to 85°C.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Analog & Data Acquisition"],"specifications":{"PLL":"Yes","Type":"Jitter Attenuator","Input":"CML, CMOS, LVDS, LVPECL","Output":"CML, LVDS, LVPECL","Package":"Tape & Reel (TR); Cut Tape (CT)","Mounting Type":"Surface Mount","Package / Case":"68-VFQFN Exposed Pad, CSP","Frequency - Max":"3.2GHz","lifecycle_stage":"eol_hot","Voltage - Supply":"3.135V ~ 3.465V","Divider/Multiplier":"Yes/No","Number of Circuits":"1","Ratio - Input:Output":"4:14","Operating Temperature":"-40°C ~ 85°C","Supplier Device Package":"68-LFCSP-VQ (10x10)","Differential - Input:Output":"Yes/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$39.52","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$39.52000","currency":"USD"},{"qty":10,"price":"$36.45300","currency":"USD"},{"qty":25,"price":"$34.81480","currency":"USD"},{"qty":100,"price":"$31.12840","currency":"USD"},{"qty":250,"price":"$29.69484","currency":"USD"},{"qty":500,"price":"$28.98000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/7fb286b97d6779c25627762930eb24c8.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the equivalent or replacement for HMC7044LP10BETR?","answer":"The closest functional peer is the HMC7043LP7FETR, which is also a PLL-based clock buffer with a 3.2 GHz maximum frequency and LVDS/LVPECL outputs, but has a 1:14 input-to-output ratio instead of 4:14. The HMC7044LP10BETR offers more input flexibility with four reference inputs versus one on the HMC7043."},{"question":"Can HMC7044LP10BETR be used for clock cleaning?","answer":"Yes, the HMC7044LP10BETR is specifically a jitter attenuator — its PLL is designed to clean a noisy reference clock and output a low-jitter version. The 3.2 GHz maximum frequency covers high-speed ADC/DAC and SERDES reference clocks."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/analog-devices/HMC7044LP10BETR","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/analog-devices/HMC7044LP10BETR when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}