{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"GAL16V8C-7LP","brand":"Lattice Semiconductor Corporation","brandSlug":"lattice-semiconductor-corporation","productSlug":"GAL16V8C-7LP","canonicalUrl":"https://icboms.com/lattice-semiconductor-corporation/GAL16V8C-7LP","factsUrl":"https://icboms.com/api/mcp/products/GAL16V8C-7LP","rawCanonicalId":null},"summary":{"shortDescription":"Lattice Semiconductor Corporation GAL® 16V8 series, EE PLD, 7.5 ns, 8 macrocells, 4.75 V ~ 5.25 V input, 20-DIP (0.300\", 7.62 mm), Through Hole, Bulk.","salesMarkdown":"## Speed bin and logic capacity for legacy 5 V boards The GAL16V8C-7LP is an electrically erasable PLD from Lattice's GAL 16V8 family, delivering a 7.5 ns propagation delay from input to combinatorial output — the ceiling for registered logic paths operating from a 5 V supply rail (4.75 V ~ 5.25 V). Eight macrocells, each configurable as registered or combinatorial, provide enough density to absorb a handful of 74-series glue-logic packages or replace a small PAL/GAL design without a board respin. ## Package and board-fit for through-hole sockets Housed in a 20-pin PDIP (0.300\" body width), the part drops into standard 0.100\" pitch DIP sockets or through-hole solder pads — the same footprint used by the original PALCE16V8 and GAL16V8 generations. The 7.5 ns speed bin is one notch slower than the 5 ns GAL16V8C-5LP but faster than the 12 ns GAL16V8Z-12QP; all three share the same 20-DIP pinout and macrocell architecture, so a board designed for one can accept the others without layout changes. ## Lifecycle and compliance reality RoHS non-compliant: the 20-DIP package uses tin-lead plating (exempt under RoHS Annex III for lead in high-melting-temperature solders). Buyers requiring lead-free finish should verify the specific date-code or request the RoHS-compliant variant if one exists.","metaTitle":"Lattice GAL16V8C-7LP EE PLD, 7.5 ns, 8 Macrocells, 20-DIP","metaDescription":"GAL16V8C-7LP from Lattice Semiconductor — 7.5 ns propagation delay, 8 macrocells, 5 V supply, 20-pin PDIP. Active production, sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":"GAL® 16V8","packageCase":null,"mountingType":null,"rohsStatus":"RoHS non-compliant","productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Lattice Semiconductor Corporation","Speed":"7.5 ns","Series":"GAL® 16V8","Package":"Bulk","Mounting Type":"Through Hole","Package / Case":"20-DIP (0.300\\\", 7.62mm)","Product Status":"Active","Voltage - Input":"4.75V ~ 5.25V","lifecycle_stage":"unknown","Programmable Type":"EE PLD","Number of Macrocells":"8","Supplier Device Package":"20-PDIP"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$1.3100","priceTiers":[{"qty":229,"price":"$1.31000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/96971cfc2d366f13328d4247aadb7298.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/GAL16V8C-7LP/alternatives.json"},"ai":{"faq":[{"question":"Will GAL16V8C-7LP drop in as a replacement for GAL16V8C-5LP?","answer":"Yes — same 20-DIP pinout, same 8-macrocell architecture, same 5 V supply range. The only difference is the speed: 7.5 ns vs 5 ns propagation delay. If the original design's timing closure allowed 7.5 ns, the swap is direct."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/lattice-semiconductor-corporation/GAL16V8C-7LP","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/lattice-semiconductor-corporation/GAL16V8C-7LP when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}