{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570T144C4N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570T144C4N","canonicalUrl":"https://icboms.com/intel/EPM570T144C4N","factsUrl":"https://icboms.com/api/mcp/products/EPM570T144C4N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570T144C4N, 440 macrocells, 5.4 ns tpd(1) max, 116 I/O, 144-LQFP, 2.5V/3.3V internal supply, 0°C~85°C, Tray.","salesMarkdown":"## 440 macrocells at 5.4 ns — right-sizing the glue logic The Intel EPM570T144C4N is a MAX® II CPLD with 440 macrocells and a 5.4 ns maximum propagation delay (tpd(1)). That delay figure means combinatorial decisions propagate from pin to pin in under 6 ns — fast enough to decode address lines, generate chip selects, or latch data without adding a wait state on a 100 MHz bus. With 116 I/O in a 144-LQFP (20x20 mm body), this part replaces a board full of 74-series logic or a handful of smaller PALs. The 570 logic elements back the macrocell count, giving you the fabric to absorb a few state machines alongside the decode logic. ## Dual-voltage supply and instant-on operation The I/O banks can be configured to match the voltage of the connected logic — no level translator needed for a 3.3 V flash or a 1.8 V SRAM interface. Being a CPLD, it is non-volatile and instant-on: the configuration is stored in flash cells on-chip, so the I/O pins assume their programmed state within microseconds of power reaching the VCC threshold. No external configuration memory, no boot time — the part is ready before the reset line on the attached processor de-asserts. ## Active production — sourcing posture The part is also available in tray packaging as listed.","metaTitle":"Intel EPM570T144C4N MAX II CPLD, 440 macrocells, 5.4 ns","metaDescription":"Intel EPM570T144C4N MAX II CPLD, 440 macrocells, 5.4 ns tpd, 116 I/O, 144-TQFP. Active production, sourced to order. Request a quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"116","Package / Case":"144-LQFP","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"144-TQFP (20x20)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$300.0000","stockQuantity":26,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the propagation delay of the EPM570T144C4N?","answer":"The maximum pin-to-pin propagation delay (tpd(1)) is 5.4 ns. This is the combinatorial delay from any input to any output through a single logic level."},{"question":"What package does the EPM570T144C4N come in?","answer":"It is supplied in a 144-lead LQFP (low-profile quad flat pack) with a 20x20 mm body, designated as 144-TQFP (20x20) in the supplier device package field."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570T144C4N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570T144C4N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-22T19:45:10.375Z","lastPublished":"2026-07-22T19:45:10.375Z","indexable":true}}