{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570T100I5N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570T100I5N","canonicalUrl":"https://icboms.com/intel/EPM570T100I5N","factsUrl":"https://icboms.com/api/mcp/products/EPM570T100I5N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570T100I5N, 440 macrocells, 570 logic elements, 76 I/O, 5.4 ns tpd1, -40°C to 100°C, 100-TQFP tray.","salesMarkdown":"## 440 macrocells, instant-on, industrial temp — right-sized glue logic The Intel EPM570T100I5N is a MAX® II CPLD with 440 macrocells and 570 logic elements — enough density to absorb a board full of 74-series logic or handle power-up sequencing, bus arbitration, and address decoding without reaching for an SRAM-based FPGA that needs a configuration load. It is in-system programmable via JTAG, so the logic image stays in the non-volatile flash cells and the device is operational the instant power rails are stable — do you really need an FPGA for that? The 5.4 ns pin-to-pin propagation delay (tpd1 max) sets the combinational throughput ceiling — for registered logic the internal clock-to-output path is faster, but for purely combinatorial paths this is the figure that governs setup timing at the receiving flip-flop. ## Dual supply, industrial temperature, active lifecycle The 100-TQFP tray packaging means it ships in the standard anti-static tray; moisture sensitivity level is typically MSL 3 for this package family, so a bake before reflow is required if the floor life is exceeded. ## Sourcing and procurement — active, quoted to order If your board sees a cold start below freezing or sits near a heat source, the I5N is the correct BOM line.","metaTitle":"Intel EPM570T100I5N MAX II CPLD, 440 macrocells, 5.4 ns","metaDescription":"Intel EPM570T100I5N MAX II CPLD, 440 macrocells, 5.4 ns tpd1, 76 I/O, -40 to 100°C, 100-TQFP. Active production, sourced to order. Request a quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"76","Package / Case":"100-TQFP","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"-40°C~100°C(TJ)","Supplier Device Package":"100-TQFP (14x14)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$18.0000","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the difference between EPM570T100I5N and EPM570T100C5N?","answer":"The sole difference is the operating temperature range. All other parametrics — 440 macrocells, 76 I/O, 5.4 ns tpd1, 100-TQFP package — are identical."},{"question":"Can EPM570T100I5N be used with 3.3V only?","answer":"Yes — the internal voltage supply accepts 3.3 V as one of its two supported rails (the other is 2.5 V). The core logic operates from whichever internal supply is present; the I/O banks can be assigned to a different voltage if needed, but the device itself runs on a single 3.3 V supply without issue."},{"question":"What is the footprint of EPM570T100I5N?","answer":"The package is a 100-TQFP with a 14x14 mm body and 0.5 mm pin pitch. The supplier device package is 100-TQFP (14x14)."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570T100I5N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570T100I5N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}