{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570M100I5N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570M100I5N","canonicalUrl":"https://icboms.com/intel/EPM570M100I5N","factsUrl":"https://icboms.com/api/mcp/products/EPM570M100I5N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570M100I5N, 570 logic elements, 440 macrocells, 76 I/O, 5.4 ns tpd, 2.5V/3.3V, -40°C to 100°C, 100-TFBGA, Tray.","salesMarkdown":"## MAX II CPLD — 570 LE, 5.4 ns, industrial temp The Intel EPM570M100I5N is a MAX® II family CPLD with 570 logic elements and 440 macrocells in a 100-ball TFBGA (6x6 mm) package. It delivers a 5.4 ns pin-to-pin propagation delay. ## 76 I/O in a 6x6 mm BGA — board-fit constraints The 100-TFBGA (MBGA) footprint measures 6x6 mm. That 76 user I/O count in a compact array means the board layout needs fine-trace escape routing. The 5.4 ns propagation delay (tpd1) is the combinatorial path from any pin through the logic array to any output. For address decoding, chip-select generation, or state-machine glue logic, that timing keeps the critical path under one clock cycle at 100+ MHz system clocks. The MAX II architecture uses a look-up-table (LUT) based core rather than the sum-of-products fabric of the older MAX 7000 series — so the 5.4 ns is a LUT delay, not a PAL-type AND-OR delay. If you are replacing a MAX 7000 part (e.g., EPM7128 with 7.5 ns tpd), this part is faster and denser, but the logic mapping tool (Quartus II) handles the translation.","metaTitle":"Intel EPM570M100I5N MAX II CPLD, 570 LE, 5.4 ns","metaDescription":"Intel EPM570M100I5N MAX II CPLD: 570 logic elements, 440 macrocells, 76 I/O, 5.4 ns tpd, 2.5V/3.3V, -40°C to 100°C, 100-TFBGA.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"76","Package / Case":"100-TFBGA","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"-40°C~100°C(TJ)","Supplier Device Package":"100-MBGA (6x6)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$5.9300","stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"Does EPM570M100I5N support JTAG programming?","answer":"Yes. The EPM570M100I5N is In System Programmable via the JTAG interface. Programming is done through the standard 4-pin JTAG header (TCK, TMS, TDI, TDO) using an Intel ByteBlaster or equivalent JTAG download cable."},{"question":"Can EPM570M100I5N replace EPM570F100I5N?","answer":"No, not without a PCB change. The M100I5N uses a 100-TFBGA (6x6 mm) package, while the F100I5N uses a 100-FBGA (different ball matrix). The die and logic are the same, but the ball-out differs — a board respin is required."},{"question":"What is the lead time for EPM570M100I5N?","answer":"Lead time is confirmed at quote time against an RFQ. As an active Intel CPLD, typical lead times range from several weeks to a few months depending on fab loading and order quantity. Submit an RFQ for current lead time and pricing."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570M100I5N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570M100I5N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}