{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"EPM570M100C4N","brand":"Intel","brandSlug":"intel","productSlug":"EPM570M100C4N","canonicalUrl":"https://icboms.com/intel/EPM570M100C4N","factsUrl":"https://icboms.com/api/mcp/products/EPM570M100C4N","rawCanonicalId":null},"summary":{"shortDescription":"Intel MAX® II CPLD, EPM570M100C4N, 440 macrocells, 570 logic elements, 76 I/O, 5.4 ns tpd, 100-ball MBGA (6x6 mm), 2.5V/3.3V, commercial temp.","salesMarkdown":"## 440 macrocells in a 6x6 mm BGA — where the MAX II fits The Intel EPM570M100C4N is a MAX II family CPLD packing 440 macrocells and 570 logic elements into a 100-ball MBGA package measuring 6x6 mm. That density-to-footprint ratio makes it a candidate for glue-logic consolidation on space-constrained boards where a larger TQFP or a separate FPGA would overhang the keep-out zone. With 76 user I/O and a propagation delay of 5.4 ns max (tpd1), it handles address decoding, state-machine sequencing, and bus interface translation at typical system clock rates up to about 100 MHz — the pin-to-pin delay sets the combinatorial logic ceiling, not the register toggle rate. ## Dual-rail supply and in-system programming The core runs on 2.5 V while the I/O banks accept 3.3 V, so it interfaces directly with 3.3 V peripherals without an external level shifter. In-system programmability via JTAG means the device can be programmed after soldering, which simplifies rework and field updates. The C4N speed grade (the '4' in the ordering code) corresponds to the 5.4 ns tpd — the 'N' suffix indicates lead-free (RoHS-compliant) finish. ## Commercial temp range and active lifecycle For extended or industrial temperature ranges, the 'I' grade variant (EPM570M100I5N) would be the alternative — the '5' denotes a 5.4 ns tpd with a wider temperature envelope.","metaTitle":"EPM570M100C4N Intel MAX II CPLD, 440 macrocells, 5.4 ns","metaDescription":"Intel MAX II CPLD, 440 macrocells, 5.4 ns tpd, 76 I/O, 100-ball MBGA, 2.5V/3.3V. Active production. Sourced to order per RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["FPGA / CPLD & Programmable Logic"],"specifications":{"Mfr":"Intel","Series":"MAX® II","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"76","Package / Case":"100-TFBGA","Product Status":"Active","lifecycle_stage":"eol_hot","Programmable Type":"In System Programmable","Base Product Number":"EPM570","Number of Macrocells":"440","Delay Time tpd(1) Max":"5.4 ns","Operating Temperature":"0°C~85°C(TJ)","Supplier Device Package":"100-MBGA (6x6)","Voltage Supply - Internal":"2.5V, 3.3V","Number of Logic Elements/Blocks":"570"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$69.0000","stockQuantity":23,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"What is the difference between EPM570M100C4N and EPM570M100I5N?","answer":"Both share the same 440-macrocell MAX II core and 100-ball MBGA package. The 'I' suffix extends the operating range for environments like outdoor enclosures or engine bays, while the 'C' grade is sufficient for most indoor commercial designs."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/intel/EPM570M100C4N","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/intel/EPM570M100C4N when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-22T19:45:10.375Z","lastPublished":"2026-07-22T19:45:10.375Z","indexable":true}}